參數(shù)資料
型號: BW1237X
英文描述: Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs
中文描述: BW1237X 8位30MSPS模數(shù)轉(zhuǎn)換器BW1237X |數(shù)據(jù)資料
文件頁數(shù): 5/10頁
文件大小: 137K
代理商: BW1237X
BW1237X
8BIT 30MSPS ADC
SEC ASIC
ANALOG
FUNCTIONAL
DESCRIPTION
1.
BW1237X
comprising three flash ADC each of which yields
3, 3 and 4 bits and two multiplying DAC. The
N-bit flash ADC is composed of 2
n
comparators, and multiplying DAC is composed
of
N+2
capacitors
and
amplifier.
is
a
three
step
A/D
Converter
latching
a
fully-differential
2. BW1237X operates as follows. During the first
"L" cycle of external clock the analog input data
is tracked and sampled, and the input is held
from the rising edge of the external clock, which
is fed to the first 3-bit flash ADC, and the first
multiplying DAC
(MDAC).
reconstructs a voltage corresponding to the first
3-bit flash ADC's output, and finally amplifies
the
residue
voltage
difference between the output of the first MDAC
and the reconstructed voltage by the gain of 2
2
.
The second 3-bit flash ADC, and MDAC operate
as the same manner and finally amplifies a
residue voltage by 2
2
. The third 4-bit flash ADC
converts the output of the second MDAC and
feed the result to the Digital Correction Logic
(DCL).
The
first
MDAC
which
is
the
voltage
3. BW1237X has the error correction scheme,
which handles the offset error which stems from
the mismatch between the first, second and third
flash ADC's comparator.
MAIN BLOCK DESCRIPTION
1. SAH
SAH(sample and hold) is the circuit that
samples the analog input signal and holds that
value until next sample-time. It is required that
the difference between the analog input signal
and the output signal be as small as it can be.
This SAH consists of fully differential op amp,
switching
transistors.
and
The
sampling
clocks
clocks(Q1, Q2) and sampling capacitor is 1.4pF.
SAH uses its own bias to avoid interference of
sampling
are
capacitors.
non-overlapping
any other circuit. SAH amp is designed to have
open-loop dc gain higher than 80dB and phase
margin higher than 60 degree. Its input block is
designed to be the rail-to-rail architecture using
complementary differential pair.
2. FLASH
The
flash
converter
compares
analog
signal(SAH output) with reference voltage, and
the result are transferred to MDAC and digital
correction logic block. Its 8 comparators are
fully differential. The comparators charge the
reference
voltage
at
the
(Q2) before comparing it with the SAH output
(Q1). The output during Q1 is stored at the
pre-latch block by Q1P clock signal.
sampling
capacitors
3. MDAC
MDAC is the most important block and it
governs
the
overall
performances
MDAC consists of amp, selection logic and
capacitor array (c_array). c_array is made up of
the sampling capacitors and switches. Selection
logic controls the internal switches of c_array. If
Q1 is high, selection's output is all low, the
switches of tsw1 are off and the switches of
tsw2 are all on. Therefore the capacitors of
c_array charges analog input values held at SAH
and
it is reversed during Q2 high.
of
ADC.
5 / 10
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