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參數(shù)資料
| 型號： | BW1251X |
| 英文描述： | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1251X 12位500KSPS ADC的BW1251X |數(shù)據(jù)資料 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 140K |
| 代理商： | BW1251X |
SEC ASIC
BW1251X
12bit 500KSPS ADC
MIXED
FEEDBACK REQUEST
ADC Specification
Parameter
Min
Typ
Max
Unit
Remarks
Supply voltage
V
Reference Input voltage
V
Analog Input voltage
Vpp
Operating temperature
°C
Integral non-linearity error
LSB
Differential non-linearity error
LSB
Offset voltage error (Bottom)
mV
Offset voltage error (Top)
mV
Maximum conversion rate
MSPS
Dynamic supply current
mA
Power dissipation
mW
Signal-to-noise ratio
dB
Digital output format
(Provide detailed description
& timing diagram)
What do you want to choose as power supply voltages For example, the analog VDD needs to be 5V. the
digital VDD can be 3.3V/5V.
What resolution do you need for ADC
How about conversion speed (data in
→
data out)
How many cycles do exist during the latency of ADC (pipelined delay)
What's the input range And then what do you need between single input and differential input
Can the bus interface be compatible with TTL
Could you explain external/internal pin configurations as required
Specially requested function list :
12/12
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