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參數(shù)資料
| 型號(hào)： | BW2010AGP |
| 英文描述： | Rad-hard quad 2-input NAND gate |
| 中文描述： | BW2010AGP倍頻BW2010AGP |數(shù)據(jù)資料 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 54K |
| 代理商： | BW2010AGP |
SEC ASIC
Frequency Doubler
ANALOG
4
/5
BW2010AGP
Functional Description
The frequency doubler has
clock. The internal phase locked loop (PLL) acts
The PLL maintains the phase and frequency relationship between the input clock and the
outputs by externally feeding back
FOUT to FIN.
Any change in the input will be tracked by output.
happen smoothly so no glitches will be present on any driven input.
The PLL circuitry matches rising edges of the input
Since the input to FIN skew is guaranteed to be 250ps, the part acts as a Zero delay buffer
when ignoring one Toggle F/F inertial Delay.
In this case, the output can go to 133
The Frequency Doubler
is fabricated using CMOS technology which results in lower power
consumption.
an output
synchronized
in phase
and frequency to an input
as a 4X clock multiplier and 2X Divider .
However, the change at the output will
clock and the output clock.
1
/
3
MHz with a 66
2
/
3
MHz input clock.
The 133
needs to be taken such that the clock skew across the interface is minimized.
Also, the timing registers for the outputs can be built into a custom I/O buffer.
The buffer itself needs to be carefully designed to balance the delays of the rising and falling
edges.
1
/
3
MHz clock also has to be routed to the output of the interface and proper care
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