參數(shù)資料
型號(hào): BW2017X
英文描述: Rad-hard quad 2-input open drain NAND gate
中文描述: BW2017X 3MHz的?25MHz的FSPLL BW2017X |數(shù)據(jù)資料
文件頁(yè)數(shù): 2/5頁(yè)
文件大?。?/td> 54K
代理商: BW2017X
SEC ASIC
Frequency Doubler
ANALOG
1
/5
BW2010AGP
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
VDD
DP
vddd
Digital power supply
VSS
DG
vssd
Digital ground
VDDA
AP
vdda
Analog power supply
VSSA
AG
vssa
Analog ground
VBB(VSUB)
AG
vbba
bulk ground
FIN
DI
pic_bb
PLL clock input
FILTER
AO
poa_bb
. Pump out is connected to Filter
. A capacitor is connected between the pin
and analog ground
FOUT
DO
poa_bb
Feed Back Clock Output
FOUT2X
DO
poa_bb
Frequency Doubler Clock Output
PWRDN
AI
pic_bb
PLL power down.(Enable High)
-If isn't used this pin, tied to VSSA.
CORE PIN DESCRIPTION
I/O TYPE ABBR.
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Analog Output
AP : Analog Power
AG : Analog Ground
AB : Analog Sub Bias
DP : Digital Power
DG : Digital Ground
DB : Digital Sub Bias
BD : Bidirectional Port
CORE CONFIGURATION
FIN
PWRDN
FOUT
FILT ER
BW2010AGP
Figure2.
Core Configuration
FOUT2X
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