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參數(shù)資料
| 型號(hào)： | BX80552641T2 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 3200 MHz, MICROPROCESSOR, PBGA775 |
| 封裝： | FLIP CHIP, LGA-775 |
| 文件頁數(shù)： | 36/108頁 |
| 文件大?。?/td> | 3283K |
| 代理商： | BX80552641T2 |
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Datasheet
35
Electrical Specifications
2.7.2
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).
Table 2-17 defines the possible combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the processor, chipset, and clock
synthesizer. All agents must operate at the same frequency.
The Pentium 4 processor will operate at an 800 MHz FSB frequency (selected by a 200 MHz
BCLK[1:0] frequency).
For more information about these signals, refer to Section 4.2.
2.7.3
Phase Lock Loop (PLL) and Filter
V
CCA and VCCIOPLL are power sources required by the PLL clock generators for the Pentium 4
processor silicon. Since these PLLs are analog, they require low noise power supplies for minimum
jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core
timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass
filtered from VTT.
The AC low-pass requirements, with input at VTT are as follows:
< 0.2 dB gain in pass band
< 0.5 dB attenuation in pass band < 1 Hz
> 34 dB attenuation from 1 MHz to 66 MHz
> 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2-3. For recommendations on implementing the
filter.
Table 2-17. BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
BSEL1
BSEL0
FSB Frequency
L
RESERVED
L
H
RESERVED
L
H
RESERVED
L
H
L
200 MHz
H
L
RESERVED
H
RESERVED
H
L
H
RESERVED
H
L
RESERVED
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