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0!5
User
’
s Manual
15-2
1999-08
Entering the Bootstrap Loader
The C161PI enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset.
In this case the built-in bootstrap loader is activated independent of the selected bus
mode. The bootstrap loader code is stored in a special Boot-ROM, no part of the
standard mask ROM, OTP or Flash memory area is required for this.
After entering BSL mode and the respective initialization
1)
the C161PI scans the RXD0
line to receive a zero byte, i.e. one start bit, eight
‘
0
’
data bits and one stop bit. From the
duration of this zero byte it calculates the corresponding baudrate factor with respect to
the current CPU clock, initializes the serial interface ASC0 accordingly and switches pin
TxD0 to output. Using this baudrate, an identification byte is returned to the host that
provides the loaded data.
This identification byte identifies the device to be bootet. The following codes are
defined:
55
H
:
8xC166.
A5
H
:
Previous versions of the C167 (obsolete).
B5
H
:
Previous versions of the C165.
C5
H
:
C167 derivatives.
D5
H
:
All devices equipped with identification registers.
Note: The identification byte D5
H
does not directly identify a specific derivative. This
information can in this case be obtained from the identification registers.
When the C161PI has entered BSL mode, the following configuration is automatically set
(values that deviate from the normal reset values, are
marked
):
Watchdog Timer:
Disabled
Register STKUN:
Context Pointer CP:
FA00
H
Register STKOV:
Stack Pointer SP:
FA40
H
Register BUSCON0:
Register S0CON:
8011
H
P3.10 / TXD0:
Register S0BG:
acc. to
‘
00
’
byte
DP3.10:
FA40
H
FA0C
H
0<->C
acc. to startup config.
‘
1
’
‘
1
’
Other than after a normal reset the watchdog timer is disabled, so the bootstrap loading
sequence is not time limited. Pin TXD0 is configured as output, so the C161PI can return
the identification byte.
Note: Even if the internal ROM/OTP/Flash is enabled, no code can be executed out of it.
The hardware that activates the BSL during reset may be a simple pull-down resistor on
P0L.4 for systems that use this feature upon every hardware reset. You may want to use
1)
The external host should not send the zero byte before the end of the BSL initialization time (see figure) to
make sure that it is correctly received.