參數(shù)資料
型號(hào)： C161S
廠商： INFINEON TECHNOLOGIES AG
英文描述： 16-Bit Single-Chip Microcontroller
中文描述： 16位單片機(jī)
文件頁數(shù)： 69/75頁
文件大?。?/td> 1315K
代理商： C161S
C161S
Timing Characteristics
Data Sheet
65
V1.0, 2003-11
Data float after RdCS
(no RW-delay)
1)
Address hold after
RdCS, WrCS
Data hold after WrCS
t
68
SR
–
5 +
t
F
–
TCL - 20
+ 2
t
A
+
t
F
–
1)
ns
t
55
CC -16 +
t
F
–
-16 +
t
F
ns
t
57
CC 9 +
t
F
–
TCL - 16
+
t
F
–
ns
1) RW-delay and
t
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Table 19
Demultiplexed Bus (Reduced Supply Voltage Range)
(cont
’
d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
t
A
+
t
C
+
t
F
(100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Min.
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Min.
Unit
Max.
Max.
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