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參數(shù)資料
| 型號： | C164SM |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontrol ler |
| 中文描述： | 16位單芯片Microcontrol萊爾 |
| 文件頁數(shù)： | 60/68頁 |
| 文件大?。?/td> | 1107K |
| 代理商： | C164SM |
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C164CM
C164SM
Data Sheet
56
V1.0, 2001-05
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Table 15
Description
ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time
Memory Cycle Variables
Symbol
t
A
t
C
t
F
Values
TCL
×
<ALECTL>
2TCL
×
(15 - <MCTC>)
2TCL
×
(1 - <MTTC>)
Multiplexed Bus
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
t
A
+
t
C
+
t
F
(120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
min.
ALE high time
t
5
CC
10 +
t
A
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
min.
TCL - 10
+
t
A
TCL - 16
+
t
A
TCL - 10
+
t
A
TCL - 10
+
t
A
-10 +
t
A
Unit
max.
–
max.
–
ns
Address setup to ALE
t
6
CC
4 +
t
A
–
–
ns
Address hold after ALE
t
7
CC
10 +
t
A
–
–
ns
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
t
8
CC
10 +
t
A
–
–
ns
t
9
CC
-10 +
t
A
–
–
ns
t
10
CC
–
6
–
6
ns
t
11
CC
–
26
–
TCL + 6
ns
t
12
CC
30 +
t
C
–
2TCL - 10
+
t
C
–
ns
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