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參數(shù)資料
| 型號： | C505C-2R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:5; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:18-5 |
| 中文描述： | 8位單片機 |
| 文件頁數(shù)： | 39/88頁 |
| 文件大?。?/td> | 1224K |
| 代理商： | C505C-2R |
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C505/C505C/C505A/C505CA
Data Sheet
35
12.00
CAN Controller (C505C and C505CA only)
The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all
resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the
extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the
CPU of as much overhead as possible when controlling many different message objects (up to 15).
This includes bus arbitration, resending of garbled messages, error handling, interrupt generation,
etc. In order to implement the physical layer, external components have to be connected to the
C505C/C505CA.
The internal bus interface connects the on-chip CAN controller to the internal bus of the
microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256
byte wide address range of the external data memory area (F700H to F7FFH) and can be accessed
using MOVX instructions.
Figure 15
shows a block diagram of the on-chip CAN controller.
The
TX/RX
Shift Register
holds the destuffed bit stream from the bus line to allow the parallel
access to the whole data or remote frame for the acceptance match test and the parallel transfer of
the frame to and from the Intelligent Memory.
The
Bit Stream Processor (BSP)
is a sequencer controlling the sequential data stream between
the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and
the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the
processes of reception, arbitration, transmission, and error signalling are performed according to
the CAN protocol. Note that the automatic retransmission of messages which have been corrupted
by noise or other external error conditions on the bus line is handled by the BSP.
The
Cyclic Redundancy Check Register (CRC)
generates the Cyclic Redundancy Check code to
be transmitted after the data bytes and checks the CRC code of incoming messages. This is done
by dividing the data stream by the code generator polynomial.
The
Error Management Logic (EML)
is responsible for the fault confinement of the CAN device. Its
counters, the Receive Error Counter and the Transmit Error Counter, are incremented and
decremented by commands from the Bit Stream Processor. According to the values of the error
counters, the CAN controller is set into the states error
active
, error
passive
and busoff.
The
Bit Timing Logic (BTL)
monitors the busline input RXDC and handles the busline related bit
timing according to the CAN protocol. The BTL synchronizes on a
recessive
to
dominant
busline
transition at
Start of Frame
(hard synchronization) and on any further
recessive
to
dominant
busline
transition, if the CAN controller itself does not transmit a
dominant
bit (resynchronization). The BTL
also provides programmable time segments to compensate for the propagation delay time and for
phase shifts and to define the position of the Sample Point in the bit time. The programming of the
BTL depends on the baudrate and on external physical delay times.
The
Intelligent Memory
(CAM/RAM array) provides storage for up to 15 message objects of
maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of
control and status bits. After the initial configuration, the Intelligent Memory can handle the
reception and transmission of data without further microcontroller actions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| C505CA-L | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| C505 | 8-Bit CMOS Microcontroller |
| C505CA-4RC | 8-bit Single-Chip Microcontroller (Bare Die Delivery) |
| C505CA-4EM | 8-Bit CMOS Microcontroller |
| C505L | Microcontrollers(8位微控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| C505C-2RM | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| C505CA | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit Single-Chip Microcontroller |
| C505CA-2R | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit Single-Chip Microcontroller |
| C505CA2RMCAKXUMA1 | 功能描述:IC MCU 32BIT 44MQFP 制造商:infineon technologies 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1 |
| C505CA2RMCAKXUMA2 | 功能描述:IC MCU 32BIT 44MQFP 制造商:infineon technologies 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1 |
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