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參數(shù)資料
| 型號(hào)： | C508 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數(shù)： | 33/93頁 |
| 文件大小： | 1204K |
| 代理商： | C508 |
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C508
Data Sheet
29
2000-08
Timer 2 Operation
Timer 2, which is a 16-bit-wide register, operates as a timer with its count rate derived
from the oscillator frequency. A prescaler offers the possibility of selecting a count rate
of 1/3 or 1/6 of the oscillator frequency. Thus, the 16-bit timer register (consisting of TH2
and TL2) is either incremented in every machine cycle or in every second machine cycle.
Compare Function of the Timer 2
The compare function of a timer/register combination can be described as follows. The
16-bit value stored in a compare/capture register is compared with the contents of the
timer register. If the count value in the timer register matches the stored value, an
appropriate output signal is generated at a corresponding port pin, and an interrupt is
requested.
The contents of a compare register can be regarded as “time stamp” at which a
dedicated output reacts in a predefined way (either with a positive or negative transition).
Variation of this “time stamp” somehow changes the wave of a rectangular output signal
at a port pin. As a variation of the duty cycle of a periodic signal, this may be used for
pulse width modulation as well as for a continually controlled generation of any kind of
square waveforms. Two compare modes are implemented to cover a wide range of
possible applications.
Compare Mode 0
In mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. It goes back to a low level on timer overflow. As long as
compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit
only, and not by the user. Writing to the port will have no effect.
Figure 12
shows a
functional diagram of a port latch in compare mode 0. The port latch is directly controlled
by the two signals timer overflow and compare. The input line from the internal bus and
the write-to-latch line are disconnected when compare mode 0 is enabled.
Compare mode 0 is ideal for generating pulse width modulated output signals, which in
turn can be used for digital-to-analog conversion via a filter network or by the controlled
device itself (e.g. the inductance of a DC or AC motor). Mode 0 may also be used for
providing output clocks with initially defined period and duty cycle. This is the mode
which needs the least CPU time. Once set up, the output goes on oscillating without any
CPU intervention.
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