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參數(shù)資料
| 型號： | C513-1RN |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 文件頁數(shù)： | 29/43頁 |
| 文件大小： | 692K |
| 代理商： | C513-1RN |
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C511 / C513
Semiconductor Group
29
Power Saving Modes
Two power down modes are available, the idle mode and the power down mode. In the idle mode
only the CPU will be deactivated while in the power down mode the on-chip oscillator is stopped.
The bits PDE and IDLE select the power down mode or the idle mode, respectively. If the power
down mode and the idle mode are set at the same time, power down takes precedence.
Table 15
gives a general overview of the power saving modes.
Table 15
Entering and leaving the power saving modes
In the power down mode of operation,
V
CC
can be reduced to minimize power consumption. It must
be ensured, however, that
V
CC
is not reduced before the power down mode is invoked, and that
V
CC
is restored to its normal operating level, before the power down mode is terminated. The reset signal
that terminates the power down mode also restarts the oscillator. The reset should not be activated
before
V
CC
is restored to its normal operating level and must be held active long enough to allow the
oscillator to restart and stabilize (similar to power-on reset).
Mode
Entering
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
– enabled interrupt
– Hardware Reset
CPU is gated off
CPU status registers maintain
their data.
Peripherals are active
Power Down
Mode
ORL PCON, #02H
Hardware Reset
Oscillators are stopped. Contents
of on-chip RAM and SFR’s are
maintained
(leaving power down mode means
redefinition of SFR’s contents)
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