參數(shù)資料
型號(hào): C513A-2RN
廠(chǎng)商: SIEMENS A G
元件分類(lèi): 微控制器/微處理器
英文描述: 8-Bit CMOS Microcontroller
中文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
文件頁(yè)數(shù): 38/43頁(yè)
文件大?。?/td> 692K
代理商: C513A-2RN
Semiconductor Group
38
C511 / C513
Figure 14
SSC Timing
Figure 15
External Clock Drive at XTAL1
Notes:
Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is
valid for the other cases accordingly.
In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).
In the case of master mode and CPHA = 0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the
first clock transition.
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