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參數(shù)資料
| 型號： | C513A-RN |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 文件頁數(shù)： | 26/43頁 |
| 文件大?。?/td> | 692K |
| 代理商： | C513A-RN |
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Semiconductor Group
26
C511 / C513
Additional On-Chip XRAM (not available in the C511/C511A/C513)
The C513A/C513A-H contain another 256 byte of on-chip RAM additional to the 256 byte internal
RAM. This RAM is called XRAM (‘e
X
tended
RAM
’).
The additional on-chip XRAM is logically located in the external data memory range from address
FF00H to FFFFH. The contents of the XRAM are not affected by a reset. After power up the content
is undefined, while it remains unchanged during and after reset as long as the power supply is not
turned off. The XRAM is controlled by SFR SYSCON as shown in
table 11
.
Table 11
Control of the XRAM
The XRAM is accessed as external data memory. Therefore, MOVX instruction types must be used
for accessing the XRAM. A general overview gives
table 12
.
Table 12
Accessing the XRAM
SFR SYSCON
Bit XMAP
Description
0
Reset value. Access to XRAM is disabled.
1
XRAM enabled. The signals RD and WR are not activated during MOVX
accesses in the XRAM address range.
Instruction
using
Instruction
Remarks
DPTR
(16-bit addr.)
MOVX A @DPTR
MOVX @DPTR,A
Normally the use of these instructions would use a
physically external memory. However, in the C513A/
C513A-H the XRAM is accessed if it is enabled by bit
XMAP and the 16-bit address (DPTR) is within the
XRAM address range FF00H - FFFFH.
If XRAM is enabled in the C513A/C513A-H, MOVX
instructions using Ri will always access the internal
XRAM. External data memory cycles will not be
generated in this case. If the XRAM is disabled, MOVX
instructions using Ri will generate normal external data
memory cycles.
R0/R1
(8-bit addr.)
MOVX A, @Ri
MOVX @Ri,A
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