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參數(shù)資料
| 型號： | C515C-8EM |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RW-D Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 48V; Output Voltage (Vdc): 05V; Power: 2W; DIP24 Low Profile Package; Dual Ouputs from a Single Supply; 2:1 Wide Range Voltage Input; 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protection; Low profile 7mm Height; Approved for Medical Applications; Efficiency to 85% |
| 中文描述： | 8位單片機 |
| 文件頁數(shù)： | 60/96頁 |
| 文件大?。?/td> | 1285K |
| 代理商： | C515C-8EM |
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C515C
Data Sheet
56
2003-02
Power Saving Modes
The C515C provides two basic power saving modes, the idle mode and the power down
mode. Additionally, a slow down mode is available. This power saving mode reduces the
internal clock rate in normal operating mode and it can be also used for further power
reduction in idle mode.
Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock
and are able to work. Idle mode is entered by software and can be left by an interrupt
or reset.
Power down mode
The operation of the C515C is completely stopped and the oscillator is turned off. This
mode is used to save the contents of the internal RAM with a very low standby current.
Software power down mode:
Software power down mode is entered by software
and can be left by reset or by a short low pulse at pin P3.2/INT0 (or P4.7/RXDC,
C515C-8E only).
Hardware power down mode:
Hardware power down mode is entered when the pin
HWPD is put to low level.
Slow-down mode
The controller keeps up the full operating functionality, but its normal clock frequency
is internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32
th
of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption. The slow down mode can be combined with
the idle mode.
Table 11
gives a general overview of the entry and exit conditions of the power saving
modes.
In the power down mode of operation,
V
DD
can be reduced to minimize power
consumption. It must be ensured, however, that
V
DD
is not reduced before the power
down mode is invoked, and that
V
DD
is restored to its normal operating level, before the
power down mode is terminated.
If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports,
peripherals) remains preserved. If a power saving mode is left by a hardware reset, the
microcontroller state is disturbed and replaced by the reset state of the C515C.
If WS (bit 4) is SFR PCON1 is set (C515C-8E only), pin P4.7/RXDC is alternatively
selected as wake-up pin for the software power down mode. If WS (bit 4) is SFR PCON1
is cleared (C515C-8E only), pin P3.2/INT0 is selected as wake-up pin for the software
power down mode.
For the C515C-8R, P3.2/INT0 is always selected as wake-up pin.
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