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參數(shù)資料
| 型號(hào)： | C5ENPA1-DS |
| 英文描述： | LIQUID-CRYSTAL DISPLAY DRIVERS |
| 中文描述： | ? - 5e類網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂格A1 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 164K |
| 代理商： | C5ENPA1-DS |
The programmability of the SDPs supports the diversity
of media access control (MAC) interfaces, as well as
data parsing requirements, and can support different
protocol implementations on a port-by-port basis.
The RISC Cores, programmed in C-language, are dedi-
cated to the advanced services that benefit the most
from high-level language implementations. For example,
the RISC Cores focus on higher-level forwarding tasks
such as final forwarding decision making, scheduling,
and statistics gathering. The RISC Cores are also respon-
sible for maintaining the context of the on-chip opera-
tions to ensure efficient delivery of traffic to the egress
ports with appropriate service levels applied.
The C-5e NP
’
s CPs can each be assigned to a physical
interface (up to 16 OC-3
’
s worth), aggregated together in
parallel clusters to support higher-bandwidth I/O
streams, or assigned internally as dedicated internal
coprocessors. When used for additional processing, the
CPs are linked for pipelined processing on a single data
stream. This allows processing power to be applied inde-
pendently of data rate.
POWERFUL TRAFFIC CLASSIFICATION
The C-5e NP
’
s fully integrated Table Lookup Unit (TLU) is
a high-speed, flexible classification engine that enables
a wide range of traffic classification functions and
supports multiple, different search algorithms
—
all
while providing the lookup performance that more than
supports OC-48c/STM-16 class applications. For
example, the TLU can achieve more than 46 million IPv4
lookups per second due to its extensively pipelined
architecture. Typical lookups that the TLU supports
include IPv4/IPv6 Longest Prefix Match, ATM VCI/VPIs,
Ethernet MAC/VLANs, and Multiprotocol Label
Switching (MPLS), among others. In addition to the table
lookups, the TLU can be configured to do integrated real-
time statistics counting.
The TLU is connected to 64bit, 133MHz ZBT SRAM. This
same interface can be used for connecting to an external
classification coprocessors in the rare case that you
need more extensive classification capabilities. In this
case, the TLU acts as a proxy to the external coprocessor.
ADVANCED QUALITY OF SERVICE MANAGEMENT
The C-5e NP
’
s Queue Management Unit (QMU), when in
internal mode, can support up to 512 queues to satisfy
the traffic management requirements of many applica-
tions. However, when the C-5e NP, using the QMU
’
s
external mode, is gluelessly coupled to a Motorola
’
s Traf-
fic Management Coprocessor (TMC), you can achieve a
powerful QoS management solution, including support
for both ATM and IP applications.
For more information about Motorola traffic managers,
see the
Q-5 Traffic Management Coprocessor Product
Brief
.
C-5e NP high functional
integration provides
design and programming
efficiencies
Internal Buses
Fabric
Processor
(FP)
Executive
Processor
(XP)
Host CPU
(optional)
Channel Processors
RC
8
RC
9
RC
10
RC
11
Channel Processors
RC
12
RC
13
RC
16
RC
15
Table
Lookups
Unit
(TLU)
Buffer
Mgmt.
Unit
(BMU)
Channel Processors
RC
0
RC
1
RC
2
RC
3
SDP
SDP
SDP
Channel Processors
RC
4
RC
5
RC
6
RC
7
SDP
SDP
SDP
Queue
Mgmt.
Unit
(QMU)
16/32-bit interface;
CSIX-L1, UTOPIA 2/3,
IBM PowerPRS
SRAM or
External
Traffic
Manager
(optional)
SRAM or
External
Classifier
(optional)
SDRAM
SDP
SDP
SDP
SDP
SDP
SDP
SDP
16 x OC-3c/STM-1
16 x 10/100 Ethernet
4 x OC-12c/STM-4
2-4 x Gigabit Ethernet
2-4 FibreChannel
SPHY/MPHY Framers
1 OC-48c/STM-16
Custom Interfaces
SDP
SDP
SDP
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù) |
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