參數(shù)資料
型號: C8051F006
廠商: Silicon Laboratories Inc
文件頁數(shù): 169/171頁
文件大?。?/td> 0K
描述: IC 8051 MCU 32K FLASH 48TQFP
標準包裝: 250
系列: C8051F00x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 托盤
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 13.4. RSTSRC: Reset Source Register
R
R/W
R
R/W
R
Reset Value
JTAGRST
CNVRSEF
C0RSEF
SWRSEF
WDTRSF
MCDRSF
PORSF
PINRSF
xxxxxxxx
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xEF
(Note: Do not use read-modify-write operations on this register.)
Bit7:
JTAGRST. JTAG Reset Flag.
0: JTAG is not currently in reset state.
1: JTAG is in reset state.
Bit6:
CNVRSEF: Convert Start Reset Source Enable and Flag
Write
0: CNVSTR is not a reset source
1: CNVSTR is a reset source (active low)
Read
0: Source of prior reset was not from CNVSTR
1: Source of prior reset was from CNVSTR
Bit5:
C0RSEF: Comparator 0 Reset Enable and Flag
Write
0: Comparator 0 is not a reset source
1: Comparator 0 is a reset source (active low)
Read
Note: The value read from C0RSEF is not defined if Comparator 0 has not been enabled as
a reset source.
0: Source of prior reset was not from Comparator 0
1: Source of prior reset was from Comparator 0
Bit4:
SWRSF: Software Reset Force and Flag
Write
0: No Effect
1: Forces an internal reset. /RST pin is not effected.
Read
0: Prior reset source was not from write to the SWRSF bit.
1: Prior reset source was from write to the SWRSF bit.
Bit3:
WDTRSF: Watchdog Timer Reset Flag
0: Source of prior reset was not from WDT timeout.
1: Source of prior reset was from WDT timeout.
Bit2:
MCDRSF: Missing Clock Detector Flag
0: Source of prior reset was not from Missing Clock Detector timeout.
1: Source of prior reset was from Missing Clock Detector timeout.
Bit1:
PORSF: Power-On Reset Force and Flag
Write
0: No effect
1: Forces a Power-On Reset. /RST is driven low.
Read
0: Source of prior reset was not from POR.
1: Source of prior reset was from POR.
Bit0:
PINRSF: HW Pin Reset Flag
0: Source of prior reset was not from /RST pin.
1: Source of prior reset was from /RST pin.
97
Rev. 1.7
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