參數(shù)資料
型號： C8051F010-GQ
廠商： Silicon Laboratories Inc
文件頁數(shù)： 156/171頁
文件大小： 0K
描述： IC 8051 MCU 32K FLASH 64TQFP
產品培訓模塊： Serial Communication Overview
標準包裝： 160
系列： C8051F01x
核心處理器： 8051
芯體尺寸： 8-位
速度： 20MHz
連通性： SMBus（2 線/I²C），SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 8x10b; D/A 2x12b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
產品目錄頁面： 621 (CN2011-ZH PDF)
其它名稱： 336-1191
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10.5.
Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the
CPU while leaving the external peripherals and internal clocks active.
In Stop mode, the CPU is halted, all
interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since
clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle.
Stop mode consumes the least power.
describes the Power Control Register (PCON) used to control the CIP-51’s power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management
of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog
peripheral can be disabled when not in use and put into low power mode. Digital peripherals, such as timers or
serial buses, draw little power whenever they are not in use. Turning off the oscillator saves even more power, but
requires a reset to restart the MCU.
10.5.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the
instruction that sets the bit completes.
All internal registers and memory maintain their original data. All analog
and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt or /RST is asserted. The assertion of an enabled interrupt will
cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU will resume operation. The pending
interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the
instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal
or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future
interrupt occurs. Any instructions that set the IDLE bit should be followed by an instruction that has 2 or more op-
code bytes, for example:
// in ‘C’:
PCON |= 0x01;
// set IDLE bit
PCON = PCON;
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
; set IDLE bit
MOV PCON, PCON
; ... followed by a 3-cycle dummy instruction
If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This
feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the
PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle
mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional
power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake
up the system. Refer to Section 13.8 Watchdog Timer for more information on the use and configuration of the
WDT.
10.5.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets
the bit completes.
In Stop mode, the CPU and oscillators are stopped, effectively shutting down all digital
peripherals. Each analog peripheral must be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and
begins program execution at address 0x0000.
85
Rev. 1.7
相關PDF資料
PDF描述
VE-B5Z-IY-F4 CONVERTER MOD DC/DC 2V 20W
ISL43144IR IC SWITCH QUAD SPST 16QFN
ISL43143IR IC SWITCH QUAD SPST 16QFN
VI-250-IY-F3 CONVERTER MOD DC/DC 5V 50W
VI-250-IY-F1 CONVERTER MOD DC/DC 5V 50W
相關代理商/技術參數(shù)
參數(shù)描述
C8051F010-GQR 功能描述:8位微控制器 -MCU 32KB 10ADC 64Pin MCU Tape and Reel RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F010R 功能描述:8位微控制器 -MCU C 10Bit 64Pin RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F010TB 功能描述:開發(fā)板和工具包 - 8051 With C8051F010 MCU RoHS:否 制造商:Silicon Labs 產品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
C8051F010-TB 功能描述:BOARD PROTOTYPING W/C8051F010 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產零件編號 系列:- 標準包裝:1 系列:- 類型:MCU 適用于相關產品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F011 功能描述:8位微控制器 -MCU 32KB 10ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*