Page 155
C8051F060/1/2/3
A
NORMAION
XTAL2
Advanced
Information
13.
RESET SOURCES
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state,
the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External port pins are forced to a known configuration
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data mem-
ory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is
reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pull-ups which take the external I/O pins
to a high state. The external I/O pins do not go high immediately, but will go high within four system clock cycles
after entering the reset state. This allows power to be conserved while the part is held in reset. For VDD Monitor
resets, the /RST pin is driven low until the end of the VDD reset timeout.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator
running at its lowest frequency. Refer to Section “
14. OSCILLATORS
” on page
161
for information on selecting
and configuring the system clock source. The Watchdog Timer is enabled using its longest timeout interval (see Sec-
tion “
13.7. Watchdog Timer Reset
” on page
157
). Once the system clock source is stable, program execution begins
at location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on, power-fail, external /RST pin, external
CNVSTR2 signal, software command, Comparator0, Missing Clock Detector, and Watchdog Timer. Each reset
source is described in the following sections.
WDT
XTAL1
OSC
Internal
Clock
Generator
System
Clock
CIP-51
Microcontroller
Core
Missing
Clock
Detector
(one-
shot)
W
S
Software Reset
Extended Interrupt
Handler
Clock Select
/RST
+
-
VDD
Supply
Reset
Timeout
VDD Monitor
reset enable
(wired-OR)
System Reset
Supply
Monitor
PRE
Reset
Funnel
+
-
CP0+
Comparator0
CP0-
(Port
I/O)
Crossbar
CNVSTR2
(CNVSTR
reset
enable)
(CP0
reset
enable)
EN
W
E
EN
M
E
(wired-OR)
Figure 13.1. Reset Sources