參數(shù)資料
型號(hào)： C8051F012
廠商： Silicon Laboratories Inc
文件頁數(shù)： 30/171頁
文件大小： 0K
描述： IC 8051 MCU 32K FLASH 32LQFP
標(biāo)準(zhǔn)包裝： 250
系列： C8051F01x
核心處理器： 8051
芯體尺寸： 8-位
速度： 20MHz
連通性： SMBus（2 線/I²C），SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 8
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-LQFP
包裝： 托盤
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
17.2.
Operation
Only a SPI master device can initiate a data transfer. The SPI is placed in master mode by setting the Master Enable
flag (MSTEN, SPI0CN.1). Writing a byte of data to the SPI data register (SPI0DAT) when in Master Mode starts a
data transfer. The SPI master immediately shifts out the data serially on the MOSI line while providing the serial
clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an
interrupt request is generated when the SPIF flag is set. The SPI master can be configured to shift in/out from one
to eight bits in a transfer operation in order to accommodate slave devices with different word lengths. The SPIFRS
bits in the SPI Configuration Register (SPI0CFG.[2:0]) are used to select the number of bits to shift in/out in a
transfer operation.
While the SPI master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously
transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. The data
byte received from the slave replaces the data in the master’s data register. Therefore, the SPIF flag serves as both a
transmit-complete and receive-data-ready flag. The data transfer in both directions is synchronized with the serial
clock generated by the master. Figure 17.3 illustrates the full-duplex operation of an SPI master and an addressed
slave.
Figure 17.3. Full Duplex Operation
Receive Buffer
0
1
2
3
4
5
6
7
SPI SHIFT REGISTER
SLAVE DEVICE
MOSI
MISO
NSS
Receive Buffer
0
1
2
3
4
5
6
7
SPI SHIFT REGISTER
MASTER DEVICE
MOSI
MISO
NSS
VDD
Baud Rate
Generator
SCK
Px.y
The SPI data register is double buffered on reads, but not on a write. If a write to SPI0DAT is attempted during a
data transfer, the WCOL flag (SPI0CN.6) will be set to logic 1 and the write is ignored. The current data transfer
will continue uninterrupted. A read of the SPI data register by the system controller actually reads the receive
buffer. If the receive buffer still holds unread data from a previous transfer when the last bit of the current transfer
is shifted into the SPI shift register, a receive overrun occurs and the RXOVRN flag (SPI0CN.4) is set to logic 1.
The new data is not transferred to the receive buffer, allowing the previously received data byte to be read. The data
byte causing the overrun is lost.
When the SPI is enabled and not configured as a master, it will operate as an SPI slave. Another SPI device acting
as a master will initiate a transfer by driving the NSS signal low. The master then shifts data out of the shift register
on the MOSI pin using the its serial clock. The SPIF flag is set to logic 1 at the end of a data transfer (when the
NSS signal goes high).
The slave can load its shift register for the next data transfer by writing to the SPI data
register. The slave must make the write to the data register at least one SPI serial clock cycle before the master
starts the next transmission. Otherwise, the byte of data already in the slave’s shift register will be transferred.
Multiple masters may reside on the same bus. A Mode Fault flag (MODF, SPI0CN.5) is set to logic 1 when the SPI
is configured as a master (MSTEN = 1) and its slave select signal NSS is pulled low. When the Mode Fault flag is
set, the MSTEN and SPIEN bits of the SPI control register are cleared by hardware, thereby placing the SPI module
125
Rev. 1.7
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
C8051F012/005 制造商:Silicon Laboratories Inc 功能描述:
C8051F012-GQ 功能描述:8位微控制器 -MCU 32KB 10ADC 32P MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
C8051F012-GQR 功能描述:8位微控制器 -MCU 32KB 10ADC 32Pin MCU Tape and Reel RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
C8051F012-PX0005GQ 制造商:Silicon Laboratories Inc 功能描述:
C8051F012R 功能描述:8位微控制器 -MCU C 10Bit 32Pin RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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