參數(shù)資料
型號： C8051F015R
廠商： Silicon Laboratories Inc
文件頁數(shù)： 25/171頁
文件大小： 0K
描述： IC 8051 MCU 32K FLASH 64TQFP
標(biāo)準(zhǔn)包裝： 1
系列： C8051F01x
核心處理器： 8051
芯體尺寸： 8-位
速度： 25MHz
連通性： SMBus（2 線/I²C），SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 剪切帶 (CT)
其它名稱： 336-1030-1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
16.6.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received.
Data remains stable in the register as long as SI is set to logic 1. Software can safely read or write to the data
register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is
enabled and the SI flag is cleared to logic 0 since the hardware may be in the process of shifting a byte of data in or
out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is
located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted
in. Therefore, SMB0DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration,
the transition from master transmitter to slave receiver is made with the correct data in SMB0DAT.
Figure 16.6. SMB0DAT: SMBus Data Register
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC2
Bits7-0: SMB0DAT: SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial
interface or a byte that has just been received on the SMBus serial interface. The CPU can
read from or write to this register whenever the SI serial interrupt flag (SMB0CN.3) is set
to logic one. The serial data in the register remains stable as long as the SI flag is set.
When the SI flag is not set, the system may be in the process of shifting data in/out and the
CPU should not attempt to access this register.
16.6.4. Address Register
The SMB0ADR Address register holds the slave address for the SMBus interface. In slave mode, the seven most-
significant bits hold the 7-bit slave address. The least significant bit, bit 0, is used to enable the recognition of the
general call address (0x00). If bit 0 is set to logic 1, the general call address will be recognized. Otherwise, the
general call address is ignored. The contents of this register are ignored when the SMBus hardware is operating in
master mode.
Figure 16.7. SMB0ADR: SMBus Address Register
R/W
Reset Value
SLV6
SLV5
SLV4
SLV3
SLV2
SLV1
SLV0
GC
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC3
Bits7-1: SLV6-SLV0: SMBus Slave Address.
These bits are loaded with the 7-bit slave address to which the SMBus will respond when
operating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the
address and corresponds to the first bit of the address byte received on the SMBus.
Bit0:
GC: General Call Address Enable.
This bit is used to enable general call address (0x00) recognition.
0: General call address is ignored.
1: General call address is recognized.
Rev. 1.7
120
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