參數(shù)資料
型號: C8051F016R
廠商: Silicon Laboratories Inc
文件頁數(shù): 131/171頁
文件大?。?/td> 0K
描述: IC 8051 MCU 32K FLASH 48TQFP
標準包裝: 1
系列: C8051F01x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10b; D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1031-1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10. CIP-51 CPU
The MCUs’ system CPU is the CIP-51.
The CIP-51 is fully compatible with the MCS-51
TM instruction set.
Standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of
all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section
19), a full-duplex UART (see description in Section 18), 256 bytes of internal RAM, 128 byte Special Function
Register (SFR) address space (see Section 10.3), and four byte-wide I/O Ports (see description in Section 14). The
CIP-51 also includes on-chip debug hardware (see description in Section 21), and interfaces directly with the
MCUs’ analog and digital subsystems providing a complete data acquisition or control-system solution in a single
integrated circuit.
Features
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram).
The CIP-51
includes the following features:
-
Fully Compatible with MCS-51 Instruction Set
-
Reset Input
-
25 MIPS Peak Throughput with 25MHz Clock
-
Power Management Modes
-
0 to 25MHz Clock Frequency (on ‘F0x5/6/7)
-
On-chip Debug Circuitry
-
Four Byte-Wide I/O Ports
-
Program and Data Memory Security
-
Extended Interrupt Handler
Figure 10.1. CIP-51 Block Diagram
DATA BUS
TMP1
TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DAT
A
BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE
POWER CONTROL
REGISTER
DAT
A
BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
B REGISTER
D8
ACCUMULATOR
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
D8
STACK POINTER
D8
Rev. 1.7
62
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