
C8051F040/1/2/3/4/5/6/7
24
Rev. 1.5
Figure 1.4. C8051F045/7 Block Diagram
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
VDD
DGND
/RST
XTAL1
XTAL2
P2.0
P2.7
P0.0
P0.7
VREF
AIN0.0
VREF
UART0
MONEN
WDT
VREFA
P7 Latch
P5 Latch
P6 Latch
P5
DRV
P6
DRV
P4
DRV
Addr [7:0]
Addr [15:8]
Ctrl Latch
Data Latch
A
M
U
X
8:2
HVAIN+
HVAIN-
HVREF
HVCAP
HVAMP
TEMP
SENSOR
P0
Drv
P1
Drv
P2
Drv
P3
Drv
Port
0,1,2,3
&4
Latches
CAN
2.0B
CANTX
8
0
5
1
C
o
r
e
Reset
A
M
U
X
Prog
Gain
ADC
100 ksps
(10-Bit)
32x136
CANRAM
256 byte
RAM
4 kB
RAM
P3.0
P3.7
P1.0
P1.7
64/32 kB
Flash
System
Clock
Internal
Oscillator
External
Oscillator
Circuit
VDD
Monitor
C
R
O
S
B
A
R
Data [7:0]
Address [15:0]
Bus Control
Digital Power
Memories
Port 4 <from crossbar>
SFR Bus
P7
DRV
Debug HW
Boundary Scan
JTAG
Logic
TCK
TMS
TDI
TDO
P2.7
P2.6
+
-
CP0
P2.3
P2.2
+
-
CP1
P2.5
P2.4
+
-
CP2
AIN0.3
AIN0.2
AIN0.1
CANRX
External Memory Data
Bus
AGND
AV+
Analog Power