
C8051F060/1/2/3/4/5/6/7
Rev. 1.2
321
26.1.1. EXTEST Instruction
The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all
the device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.
26.1.2. SAMPLE Instruction
The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of
the scan-path latches.
26.1.3. BYPASS Instruction
The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data reg-
ister.
26.1.4. IDCODE Instruction
The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.
87, 89, 91, 93, 95,
97, 99, 101
Capture
P6.n input from pin (follows P0.n numbering scheme)
Update
P6.n output to pin (follows P0.n numbering scheme)
102, 104, 106,
108, 110, 112, 114,
116
Capture
P7.n output enable from MCU (follows P0.n numbering scheme)
Update
P7.n output enable to pin (follows P0.n numbering scheme)
103, 105, 107,
109, 111, 113, 115,
117
Capture
P7.n input from pin (follows P0.n numbering scheme)
Update
P7.n output to pin (follows P0.n numbering scheme)
Not connected to pins in this device package.
Table 26.2. Boundary Data Register Bit Definitions (C8051F061/3/5/7) (Continued)
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
Bit
Action
Target
Figure 26.2. DEVICEID: JTAG Device ID Register
Version = 0000b
Part Number = 0000 0000 0000 0110b (C8051F060/1/2/3/4/5/6/7)
Manufacturer ID = 0010 0100 001b (Silicon Labs)
Reset Value
Version
Part Number
Manufacturer ID
1
0xn0006243
Bit31
Bit28 Bit27
Bit12 Bit11
Bit1
Bit0