參數(shù)資料
型號(hào): C8051F206-GQR
廠商: Silicon Laboratories Inc
文件頁數(shù): 73/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
產(chǎn)品培訓(xùn)模塊: Serial Communication Overview
標(biāo)準(zhǔn)包裝: 500
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 帶卷 (TR)
配用: 336-1237-ND - DEV KIT FOR C8051F206
C8051F2xx
32
Rev. 1.6
5.
ADC (8-Bit, C8051F220/1/6 Only)
Description
The ADC subsystem for the C8051F220/1/6 consists of configurable analog multiplexer (AMUX), a pro-
grammable gain amplifier (PGA), and a 100ksps, 8-bit successive-approximation-register ADC with inte-
grated track-and-hold and programmable window detector (see Figure 5.1).
The AMUX, PGA, Data
Conversion Modes, and Window Detector are all configurable under software control via the Special Func-
tion Register's shown in Figure 5.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, SFR Definition 5.3) is set to 1. The ADC sub-
system is in low power shutdown when this bit is 0.
Figure 5.1. 8-Bit ADC Functional Block Diagram
5.1.
Analog Multiplexer and PGA
Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the
desired analog input pin. (See SFR Definition 5.1). When the AMUX is enabled, the user selects which
port is to be used (bits PRTSL0-1), and then the pin in the selected port (bits PINSL0-2) to be the analog
input.
The table in ?? shows AMUX functionality by channel for each possible configuration. The PGA amplifies
the AMUX output signal by an amount determined by the states of the AMPGN2-0 bits in the ADC Config-
uration register, ADC0CF (SFR Definition 5.2). The PGA can be software-programmed for gains of 0.5, 1,
2, 4, 8 or 16. It defaults to a gain of 1 on reset.
8-Bit
SAR
ADC
RE
F
+
-
VDD
8
32-to-1
AMUX
VDD
ADCEN
S
YSC
L
K
X
AIN0
AIN31
ADBUSY(w)
C
onve
rsi
on
S
tar
t
AMX0SL
PI
N
S
L0
PI
N
S
L1
PI
N
S
L2
PRT
SL
0
ADC0CF
AMPGN0
AMPGN1
AMPGN2
A
D
CS
C0
A
D
CS
C1
A
D
CS
C2
ADC0CN
AD
L
J
ST
AD
W
IN
T
ADS
T
M
0
ADS
T
M
1
AD
BU
S
Y
A
DCI
NT
ADC
T
M
A
DCE
N
A
DC0
H
AM
X
EN
PRT
SL
1
VDD
VREF
GND
T2 OV
..
.
ADC0LTH
ADC0GTH
16
8
ADWINT
AIN0-31 are port 0-3
pins -- any external
port pin may be configured as an
analog input
GND
Dig
Comp
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