參數(shù)資料
型號: C8051F236
廠商: Silicon Laboratories Inc
文件頁數(shù): 82/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 托盤
C8051F2xx
40
Rev. 1.6
6.
ADC (12-Bit, C8051F206 Only)
Description
The ADC subsystem for the C8051F206 consists of configurable analog multiplexer (AMUX), a program-
mable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC with integrated
track-and-hold and programmable window detector (see Figure 6.1). The AMUX, PGA, Data Conversion
Modes, and Window Detector are all configurable under software control via the Special Function Regis-
ter's shown in Figure 6.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the
ADCEN bit in the ADC Control register (ADC0CN, Figure 6.5) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0.
Figure 6.1. 12-Bit ADC Functional Block Diagram
6.1.
Analog Multiplexer and PGA
Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the
desired analog input pin. (See SFR Definition 5.1). When the AMUX is enabled, the user selects which
port is to be used (bits PRTSL0–1), and then the pin in the selected port (bits PINSL0–2) to be the analog
input.
The PGA amplifies the AMUX output signal by an amount determined by the states of the AMPGN2–0 bits
in the ADC Configuration register, ADC0CF (SFR Definition 5.2). The PGA can be software-programmed
for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to a gain of 1 on reset.
12-Bit
SAR
ADC
RE
F
+
-
VDD
12
32-to-1
AMUX
VDD
ADCEN
S
YSC
L
K
X
AIN0
AIN31
ADBUSY(w)
C
onve
rsi
on
S
tar
t
AMX0SL
PI
N
S
L
0
PI
N
S
L
1
PI
N
S
L
2
PR
TSL
0
ADC0CF
AM
PGN
0
AM
PGN
1
AM
PGN
2
A
DCS
C
0
A
DCS
C
1
A
DCS
C
2
ADC0CN
ADLJ
ST
ADW
INT
AD
STM
0
AD
STM
1
AD
BUS
Y
ADC
INT
A
DCT
M
ADC
EN
A
DC0
H
AM
X
EN
PR
TSL
1
VDD
VREF
GND
T2 OV
..
.
ADC0LTL
ADC0LTH
24
12
ADWINT
AIN0-31 are port 0-3
pins -- any external
port pin may be configured
as an analog input
GND
AD
C0
L
ADC0GTL
ADC0GTH
Dig
Comp
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