參數(shù)資料
型號: C8051F300-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 19/178頁
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 11QFN
產(chǎn)品培訓模塊: Serial Communication Overview
標準包裝: 122
系列: C8051F30x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),UART/USART
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x8b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-VFDFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 623 (CN2011-ZH PDF)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1351-ND - KIT REF DES TEMP COMPENS RTC
336-1348-ND - KIT STARTER TOOLSTICK
336-1283-ND - KIT REF DESIGN DTMF DECODER
336-1278-ND - KIT TOOL EVAL SYS IN A USB STICK
336-1246-ND - DEV KIT F300/301/302/303/304/305
其它名稱: 336-1245
Rev. 2.9
115
C8051F300/1/2/3/4/5
13.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting,
this interrupt is generated after the ACK cycle so that software may read the received ACK value; when
receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing
ACK value. See Section “13.5. SMBus Transfer Modes” on page 123 for more details on transmission
sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section
ence.
SMBus configuration options include:
Timeout detection (SCL Low Timeout and/or Bus Free Timeout)
SDA setup and hold time extensions
Slave event enable/disable
Clock source selection
These options are selected in the SMB0CF register, as described in Section “13.4.1. SMBus Configura-
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