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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� C8051F560-TB
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 62/302闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� BOARD PROTOTYPE W/C8051F560
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
椤炲瀷锛� MCU
閬╃敤浜庣浉闂�(gu膩n)鐢�(ch菐n)鍝侊細 C8051F55x锛孋8051F56x锛孋8051F57x
鎵€鍚墿鍝侊細 鏉�
閰嶇敤锛� 336-1691-ND - KIT DEVELOPMENT FOR C8051F560
鍏跺畠鍚嶇ū锛� 336-1694
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C8051F55x/56x/57x
154
Rev. 1.1
Table 17.2. AC Parameters for External Memory Interface
Parameter
Description
Min*
Max*
Units
TACS
Address/Control Setup Time
0
3 x TSYSCLK
ns
TACW
Address/Control Pulse Width
1 x TSYSCLK
16 x TSYSCLK
ns
TACH
Address/Control Hold Time
0
3 x TSYSCLK
ns
TALEH
Address Latch Enable High Time
1 x TSYSCLK
4 x TSYSCLK
ns
TALEL
Address Latch Enable Low Time
1 x TSYSCLK
4 x TSYSCLK
ns
TWDS
Write Data Setup Time
1 x TSYSCLK
19 x TSYSCLK
ns
TWDH
Write Data Hold Time
0
3 x TSYSCLK
ns
TRDS
Read Data Setup Time
20
ns
TRDH
Read Data Hold Time
0
ns
*Note:
TSYSCLK is equal to one period of the device system clock (SYSCLK).
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C8051F561-IM 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 50 MIPS 32 kB 2 kB CAN2 SPI UART RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
C8051F561-IMR 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 50 MIPS 32 kB 2 kB CAN2.0 SPI RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
C8051F561-IQ 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 50 MIPS 32 kB 2 kB CAN2 SPI UART RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
C8051F561-IQR 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 50 MIPS 32 kB 2 kB CAN2.0 SPI RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
C8051F562-IM 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 50 MIPS 32 kB 2 kB LIN 2.1 SPI UART RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT