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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� C8051F800DK
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 191/250闋�
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Rev. 1.0
45
C8051F80x-83x
Table 7.13. Comparator Electrical Characteristics
VDD = 3.0 V, 鈥�40 to +85 掳C unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Response Time:
Mode 0, Vcm* = 1.5 V
CP0+ 鈥� CP0鈥� = 100 mV
鈥�
220
鈥�
ns
CP0+ 鈥� CP0鈥� = 鈥�100 mV
鈥�
225
鈥�
ns
Response Time:
Mode 1, Vcm* = 1.5 V
CP0+ 鈥� CP0鈥� = 100 mV
鈥�
340
鈥�
ns
CP0+ 鈥� CP0鈥� = 鈥�100 mV
鈥�
380
鈥�
ns
Response Time:
Mode 2, Vcm* = 1.5 V
CP0+ 鈥� CP0鈥� = 100 mV
鈥�
510
鈥�
ns
CP0+ 鈥� CP0鈥� = 鈥�100 mV
鈥�
945
鈥�
ns
Response Time:
Mode 3, Vcm* = 1.5 V
CP0+ 鈥� CP0鈥� = 100 mV
鈥�
1500
鈥�
ns
CP0+ 鈥� CP0鈥� = 鈥�100 mV
鈥�
5000
鈥�
ns
Common-Mode Rejection Ratio
鈥�
1
4
mV/V
Positive Hysteresis 1
Mode 2, CP0HYP1鈥�0 = 00b
鈥�
0
1
mV
Positive Hysteresis 2
Mode 2, CP0HYP1鈥�0 = 01b
2
5
10
mV
Positive Hysteresis 3
Mode 2, CP0HYP1鈥�0 = 10b
7
10
20
mV
Positive Hysteresis 4
Mode 2, CP0HYP1鈥�0 = 11b
10
20
30
mV
Negative Hysteresis 1
Mode 2, CP0HYN1鈥�0 = 00b
鈥�
0
1
mV
Negative Hysteresis 2
Mode 2, CP0HYN1鈥�0 = 01b
2
5
10
mV
Negative Hysteresis 3
Mode 2, CP0HYN1鈥�0 = 10b
7
10
20
mV
Negative Hysteresis 4
Mode 2, CP0HYN1鈥�0 = 11b
10
20
30
mV
Inverting or Non-Inverting Input
Voltage Range
鈥�0.25
鈥�
VDD + 0.25
V
Input Offset Voltage
鈥�7.5
鈥�
7.5
mV
Power Specifications
Power Supply Rejection
鈥�
0.1
鈥�
mV/V
Powerup Time
鈥�
10
鈥�
s
Supply Current at DC
Mode 0
鈥�
20
鈥�
A
Mode 1
鈥�
8
鈥�
A
Mode 2
鈥�
3
鈥�
A
Mode 3
鈥�
0.5
鈥�
A
Note: Vcm is the common-mode voltage on CP0+ and CP0鈥�.
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