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參數(shù)資料
| 型號： | C9531 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | SMD LED Lamps |
| 中文描述： | PCIX I / O系統(tǒng)時鐘發(fā)生器與EMI控制功能 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 176K |
| 代理商： | C9531 |
PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07034 Rev. **
05/02/2001
Page 2 of 14
APPROVED PRODUCT
C9531
Pin Description
Pin No.
Pin
Name
XIN
PWR
I/O
Description
3
VDDA
I
Crystal Buffer input pin. Connects to a crystal, or an external clock
source. Serves as input clock TCLK, in Test mode.
Crystal Buffer output pin. Connects to a crystal only. When a Can
Oscillator is used or in Test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin, typically 33.33
MHz
Output Enable for clock bank. Causes the CLK (0:4) output clocks to
be in a Tri-state condition when driven to a logic low level.
A bank of Five 33.3, 66.6, 100.0 or 133.3 MHz output clocks (1x, 2x,
3x or 4x Xin clock).
When his output signal is a logic low level, it indicates that the output
clocks of the bank are locked to the input reference clock. This output
is latched.
Clock Bank selection bits. These control the clock frequency that will
be present on the outputs of the bank of buffers. See table on page
one for frequency codes and selection values.
3.3V common power supply pin for all PCI clocks CLK (0:4).
SMBus address selection input pins. See SMBus Address table, pg. 4.
4
XOUT
VDDA
O
1
REF
VDD
O
14*
OE
VDD
I
24, 23, 22,
19, 18
8
CLK(0:4)
VDDP
O
GOOD#
VDD
O
6*, 7*
S(0,1)
VDD
I
20, 25
10*, 11*,
12*
15*
VDDP
IA(0:2)
PWR
I
VDD
SSCG#
VDD
I
Enables Spread Spectrum clock modulation when at a logic low level,
see pg. 3.
Data for the internal SMBus circuitry, see pg. 4.
Clock for the internal SMBus circuitry, see pg. 4.
Power for internal analog circuitry. This supply should have a
separately decoupled current source from VDD.
Power supply for internal Core logic
Ground pins for the device
28
27
SDATA
SCLK
AVDD
VDD
VDD
-
I/O
I
I
13, 17
2
VDD
VSS
-
-
PWR
PWR
5, 9, 16, 21,
26
Note
: Pin numbers ending with a * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no
external circuitry is connected to them.
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins, their high
frequency filtering characteristic will be cancelled by the lead inductance of the trace. PWR = Power connection, I = Input, O = Output and I/O = both
input and output functionality of the pin(s).
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| C9531_04 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PCIX I/O System Clock Generator with EMI Control Features |
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