參數(shù)資料
型號： C9726AY
英文描述： ST92141 - 8/16 BIT MCU FOR 3-PHASE AC MOTOR CONTROL
中文描述： CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 48PIN |塑料
文件頁數(shù)： 10/16頁
文件大?。?/td> 119K
代理商： C9726AY
C9726
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07047 Rev. **
05/03/2001
Page 10 of 16
AC Parameters
133 MHz Host
Min
7.5
1
-
-
1
7.5
1.87
1.67
0.4
-
-
-
29.93
12.0
12.0
0.5
-
-
20.8299
100 MHz Host
Min
9.98
1
-
-
1
10.0
3.0
2.8
0.4
-
-
-
29.94
12.0
12.0
0.5
-
-
20.8299
Symbol
TPeriod
Tf
TSKEW0
TCCJ
Toff
TPeriod
THIGH
TLOW
Tr / Tf
TDelay
TSKEW1
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW2
TCCJ
TPeriod
Parameter
CPU, CPU#, CPUCS period
CPU, CPU#, CPUCS fall times
CPU to CPUCS Skew time
CPU Cycle to Cycle Jitter
CPUCS to any PCI
SDRAM[0:12] period
SDRAM[0:12] high time
SDRAM[0:12] low time
SDRAM[0:12] rise and fall times
SDRAMIN to Any SDRAM[0:12]
Any SDRAM to Any SDRAM
SDRAM[0:12] Cycle to Cycle Jitter
PCI(0:5) period
PCI(0:5) period
PCI(0:5) low time
PCI(0:5) rise and fall times
(Any PCI clock) to (Any PCI clock)
PCI(0:5) Cycle to Cycle Jitter
48MHz period ( conforms to
+167ppm max)
48MHz rise and fall times
48MHz Cycle to Cycle Jitter
24MHz period
24MHz rise and fall times
24 MHz Cycle to Cycle Jitter
REF(0:1) period
REF(0:1) rise and fall times
REF(0:1) Cycle to Cycle Jitter
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
Note 5:
This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
Note 6:
All outputs loaded as per table 5.
Note 7:
Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V. (see fig.7.)
Note 8:
Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals (fig.7) and as in fig.9 for differential
CPU clocks
Note 9:
This measurement is applicable with Spread ON or Spread OFF.
Note 10:
Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals (see fig.7)
Note 11:
Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 12:
The time specified is measured from when all VDD’s reach their respective supply rail (3.3V) till the frequency output is
stable and operating within the specifications
Note 13:
Measured from when Byte0, bit0 is toggled.
Note14:
CPUCS leads.
Max
8.0
-
-300
250
4
8.0
-
-
1.6
3.5
250
250
-
-
-
2.0
500
500
20.8333
Max
10.5
-
-300
250
4
10.5
-
-
1.6
3.5
250
250
-
-
-
2.0
500
500
20.8333
Units
nS
V/nS
pS
pS
nS
nS
nS
nS
nS
nS
pS
pS
nS
nS
nS
nS
pS
pS
nS
Notes
5, 6, 8
6
6, 8, 9,14
6, 8, 9
8
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
6, 8, 9
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
5, 6, 8
Tr / Tf
TCCJ
TPeriod
Tr / Tf
TCCJ
TPeriod
Tr / Tf
TCCJ
tpZL, tpZH
tpLZ, tpHZ
tstable
1.0
-
41.6598
1.0
-
69.8413
1.0
-
1.0
1.0
4.0
500
41.6666
4.0
500
71.0
4.0
1000
10.0
10.0
3
1.0
-
41.6598
1.0
-
69.8413
1.0
-
1.0
1.0
4.0
500
41.6666
4.0
500
71.0
4.0
1000
10.0
10.0
3
nS
pS
nS
nS
pS
nS
nS
pS
nS
nS
mS
6, 7
6, 8, 9
5, 6, 8
6, 7
6, 8, 9
5, 6, 8
6, 7
6, 8
13
13
12
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