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| 型號(hào)： | C9827JT |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器|采用TSSOP | 56PIN |塑料 |
| 文件頁(yè)數(shù)： | 13/25頁(yè) |
| 文件大?。?/td> | 170K |
| 代理商： | C9827JT |
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C9827J
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07107 Rev. **
5/24/2001
Page 13 of 25
Group Timing Relationship and Tolerances
Offset
2.5 nS
0.0 nS
2.5 nS
Tolerance
±
1.0 nS
±
1.0 nS
±
1.0 nS
Conditions
3V66 Leads PCI (un-buffered mode)
0 degrees phase shift
66B leads PCI (buffered mode)
3V66 to PCI
USB to DOT 48M Skew
66B(0:2) to PCI offset
USB and DOT 48M Phase Relationship
The 48MUSB and 48MDOT clocks are in phase. It is understood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for VCH (48MHz) operation it is also in phase with the USB and
DOT outputs.
USB48M
DOT48M
Figure 3
48MUSB and 48MDOT Phase Relationship
66IN to 66B(0:2) Buffered Prop Delay
The 66IN to 66B(0:2) output delay is shown below.
66IN
66CB0:2)
Tpd
Figure 4
66IN to 66B(0:2) Output Delay Figure
The Tpd is the prop delay from the input pin (66IN) to the output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The measurement taken at 1.5 volts.
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