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參數(shù)資料
| 型號： | C9827JY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 170K |
| 代理商： | C9827JY |
C9827J
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07107 Rev. **
5/24/2001
Page 17 of 25
PCI_STP# Clarification
The PCI_STP# signal is an active low input used for synchronous stopping and starting the PCI outputs while the rest of
the clock generator continues to function. The setup time for capturing PCI_STP# going low is 10 nsec (t
setup
). The
PCI_F (0:2) clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be
free running.
PCI_STP#
PCI_F(0:2) 33M
PCI(0:6) 33M
setup
t
Figure 7
PCI_STP# Waveform Figure
PCI_STP# - De-assertion (transition from logic ‘0’ to logic ‘1’)
The de-assertion of the PCI_STP# signal will cause all PCI(0:6) and stoppable PCI_F(0:2) clocks to resume running in a
synchronous manner within 2 PCI clock periods after PCI_STP# transitions to a high level.
Note that the PCI STOP function is controlled by 2 inputs. One is the device PCI_STP# pin number 34 and the other is
SMBus byte 0 bit 3. These 2 inputs to the function are logically ANDed. If either the external pin or the internal SMBus
register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will
return a 0 value if either of these control bits are set low thereby indicating the devices stoppable PCI clocks are not
running.
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