參數(shù)資料
型號： CA16A2Cnn
英文描述： CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
中文描述： CA16型2.5 Gb /秒的DWDM轉(zhuǎn)發(fā)器，16通道155 Mbits /秒復(fù)用器/解復(fù)用器
文件頁數(shù)： 18/30頁
文件大?。?/td> 464K
代理商： CA16A2CNN
18
Agere Systems Inc.
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Advance Data Sheet
March 2001
Timing Characteristics
Transmitter Data Input Timing
The CA16 transponder utilizes a unique FIFO to
decouple the internal and external (PIC
LK
) clocks. The
FIFO can be initialized, which allows the system
designer to have an infinite PC
LK
-to-PIC
LK
delay
through this interfacing logic (ASIC or commercial chip
set). The configuration of the FIFO is dependent upon
the I/O pins, which comprise the synch timing loop.
This loop is formed from PHERR to PHINIT and PC
LK
to PIC
LK
.
The FIFO can be thought of as a memory stack that
can be initialized by PHINT or LOCKDET. The PHERR
signal is a pointer that goes high when a potential tim-
ing mismatch is detected between PIC
LK
and the inter-
nally generated PC
LK
clock. When PHERR is fed back
to PHINIT, it initializes the FIFO so that it does not over-
flow or underflow.
The internally generated divide-by-16 clock is used to
clock-out data from the FIFO. PHINIT and LOCKDET
signals will center the FIFO after the third PIC
LK
pulse.
This is done to ensure that PIC
LK
is stable. This
scheme allows the user to have an infinite PC
LK
to
PIC
LK
delay through the ASIC. Once the FIFO is cen-
tered, the PC
LK
and PIC
LK
can have a maximum drift of
±5 ns.
During normal operation, the incoming data is passed
from the PIC
LK i
nput timing domain to the internally
generated divide-by-16 PC
LK
timing domain. Although
the frequency of PIC
LK
and PC
LK
is the same, their
phase relationship is arbitrary. To prevent errors caused
by short setup or hold times between the two domains,
the timing generator circuitry monitors the phase rela-
tionship between PIC
LK
and PC
LK
.
When an FIFO timing violation is detected, the phase
error (PHERR) signal pulses high. If the condition per-
sists, PHERR will remain high. When PHERR is fed
back into the PHINIT input (by shorting them on the
printed-circuit board [PCB]), PHINIT will initialize the
FIFO if PHINIT is held high for at least two byte clocks.
The initialization of the FIFO prevents PC
LK
and PIC
LK
from concurrently trying to read and write over the
same FIFO bank.
During realignment, one-to-three bytes (16 bits wide)
will be lost. Alternatively, the customer logic can take in
the PHERR signal, process it, and send an output to
the PHINIT input in such a way that only idle bytes are
lost during the initialization of the FIFO. Once the FIFO
has been initialized, PHERR will go inactive.
相關(guān)PDF資料
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CA16B2Cnn CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CA16A2FAA 制造商:AGERE 制造商全稱:AGERE 功能描述:CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
CA16A2FNN 制造商:AGERE 制造商全稱:AGERE 功能描述:CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
CA16B 制造商:Datak Corporation 功能描述:
CA16B2CAA 制造商:AGERE 制造商全稱:AGERE 功能描述:CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
CA16B2CNN 制造商:AGERE 制造商全稱:AGERE 功能描述:CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
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