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參數(shù)資料
| 型號(hào)： | CA3130EZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output |
| 中文描述： | OP-AMP, 15000 uV OFFSET-MAX, 15 MHz BAND WIDTH, PDIP8 |
| 封裝： | LEAD FREE, PLASTIC, MO-001-BA, DIP-8 |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大小： | 943K |
| 代理商： | CA3130EZ |
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5
Cascade-connected PMOS transistors Q2, Q4 are the
constant-current source for the input stage. The biasing circuit
for the constant-current source is subsequently described.
The small diodes D
5
through D
8
provide gate-oxide protection
against high-voltage transients, including static electricity
during handling for Q
6
and Q
7
.
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q
11
and its cascade-connected load resistance provided by
PMOS transistors Q
3
and Q
5
. The source of bias potentials
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R
2
and zener diode Z
1
serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor R
1
, diodes
D
1
through D
4
, and PMOS transistor Q
1
. A tap at the junction
of resistor R
1
and diode D
4
provides a gate-bias potential of
about 4.5V for PMOS transistors Q
4
and Q
5
with respect to
Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q
1
with respect to Terminal
7 to provide gate bias for PMOS transistors Q
2
and Q
3
. It
should be noted that Q
1
is “mirror-connected (see Note 8)” to
both Q
2
and Q
3
. Since transistors Q
1
, Q
2
, Q
3
are designed to
be identical, the approximately 200
μ
A current in Q
1
establishes a similar current in Q
2
and Q
3
as constant current
sources for both the first and second amplifier stages,
respectively.
At total supply voltages somewhat less than 8.3V, zener
diode Z
1
becomes nonconductive and the potential,
developed across series-connected R
1
, D
1
-D
4
, and Q
1
,
varies directly with variations in supply voltage.
Consequently, the gate bias for Q
4
, Q
5
and Q
2
, Q
3
varies in
accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.
Output Stage
The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
NOTE:
8. For general information on the characteristics of CMOS
transistor-pairs in linear-circuit applications, see File Number
619, data sheet on CA3600E “CMOS Transistor Array”.
3
2
-
7
4
8
1
5
6
BIAS CKT.
COMPENSATION
(WHEN REQUIRED)
A
V
≈
5X
A
≈
6000X
A
≈
30X
INPUT
+
200
μ
A
200
μ
A
1.35mA
8mA
(NOTE 5)
0mA
(NOTE 7)
V+
OUTPUT
V-
STROBE
C
C
OFFSET
NULL
CA3130
NOTES:
6. Total supply voltage (for indicated voltage gains) = 15V with input
terminals biased so that Terminal 6 potential is +7.5V above
Terminal 4.
7. Total supply voltage (for indicated voltage gains) = 15V with
output terminal driven to either supply rail.
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES
22.5
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
O
17.5
20
12.5
15
10
7.5
2.5
5
0
2.5
7.5
5
10
15
12.5
17.5
0
SUPPLY VOLTAGE: V+ = 15, V- = 0V
T
A
= 25
C
LOAD RESISTANCE = 5k
500
1k
2k
FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
CA3130, CA3130A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CA3130M | 功能描述:IC OP AMP 15MHZ BIMOS 8-SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:2pA 電壓 - 輸入偏移:1000µV 電流 - 電源:85µA 電流 - 輸出 / 通道:20mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:680 (CN2011-ZH PDF) 其它名稱:MCP6L04T-E/SLCT |
| CA3130M96 | 功能描述:IC OP AMP 15MHZ BIMOS 8-SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:2pA 電壓 - 輸入偏移:1000µV 電流 - 電源:85µA 電流 - 輸出 / 通道:20mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:680 (CN2011-ZH PDF) 其它名稱:MCP6L04T-E/SLCT |
| CA3130MZ | 功能描述:運(yùn)算放大器 - 運(yùn)放 W/ANNEAL OPAMP 15MHZ LWBIAS 0 03NA MIL RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| CA3130MZ96 | 功能描述:運(yùn)算放大器 - 運(yùn)放 W/ANNEAL OPAMP 15MHZ LWBIAS 0 03NA COMP RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| CA3130S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
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