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參數(shù)資料
| 型號： | CA3140AM |
| 廠商： | INTERSIL CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output |
| 中文描述： | OP-AMP, 5000 uV OFFSET-MAX, 4.5 MHz BAND WIDTH, PDSO8 |
| 封裝： | PLASTIC, MS-012-AA, SOIC-8 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 1042K |
| 代理商： | CA3140AM |
5
Application Information
Circuit Description
As shown in the block diagram, the input terminals may be
operated down to 0.5V below the negative supply rail. Two
class A amplifier stages provide the voltage gain, and a
unique class AB amplifier stage provides the current gain
necessary to drive low-impedance loads.
A biasing circuit provides control of cascoded constant current
flow circuits in the first and second stages. The CA3140
includes an on chip phase compensating capacitor that is
sufficient for the unity gain voltage follower configuration.
Input Stage
The schematic diagram consists of a differential input stage
using PMOS field-effect transistors (Q
9
, Q
10
) working into a
mirror pair of bipolar transistors (Q
11
, Q
12
) functioning as load
resistors together with resistors R
2
through R
5
. The mirror pair
transistors also function as a differential-to-single-ended
converter to provide base current drive to the second stage
bipolar transistor (Q
13
). Offset nulling, when desired, can be
effected with a 10k
potentiometer connected across
Terminals 1 and 5 and with its slider arm connected to Terminal
4. Cascode-connected bipolar transistors Q
2
, Q
5
are the
constant current source for the input stage. The base biasing
circuit for the constant current source is described
subsequently. The small diodes D
3
, D
4
, D
5
provide gate oxide
protection against high voltage transients, e.g., static electricity.
Second Stage
Most of the voltage gain in the CA3140 is provided by the
second amplifier stage, consisting of bipolar transistor Q
13
and its cascode connected load resistance provided by
bipolar transistors Q
3
, Q
4
. On-chip phase compensation,
sufficient for a majority of the applications is provided by C
1
.
Additional Miller-Effect compensation (roll off) can be
accomplished, when desired, by simply connecting a small
capacitor between Terminals 1 and 8. Terminal 8 is also
used to strobe the output stage into quiescence. When
terminal 8 is tied to the negative supply rail (Terminal 4) by
mechanical or electrical means, the output Terminal 6
swings low, i.e., approximately to Terminal 4 potential.
Output Stage
The CA3140 Series circuits employ a broad band output stage
that can sink loads to the negative supply to complement the
capability of the PMOS input stage when operating near the
negative rail. Quiescent current in the emitter-follower cascade
circuit (Q
17
, Q
18
) is established by transistors (Q
14
, Q
15
)
whose base currents are “mirrored” to current flowing through
diode D
2
in the bias circuit section. When the CA3140 is
operating such that output Terminal 6 is sourcing current,
transistor Q
18
functions as an emitter-follower to source current
from the V+ bus (Terminal 7), via D
7
, R
9
, and R
11
. Under these
conditions, the collector potential of Q
13
is sufficiently high to
permit the necessary flow of base current to emitter follower
Q
17
which, in turn, drives Q
18
.
When the CA3140 is operating such that output Terminal 6 is
sinking current to the V- bus, transistor Q
16
is the current
sinking element. Transistor Q
16
is mirror connected to D
6
, R
7
,
with current fed by way of Q
21
, R
12
, and Q
20
. Transistor Q
20
, in
turn, is biased by current flow through R
13
, zener D
8
, and R
14
.
The dynamic current sink is controlled by voltage level sensing.
For purposes of explanation, it is assumed that output Terminal
6 is quiescently established at the potential midpoint between
the V+ and V- supply rails. When output current sinking mode
operation is required, the collector potential of transistor Q
13
is
driven below its quiescent level, thereby causing Q
17
, Q
18
to
decrease the output voltage at Terminal 6. Thus, the gate
terminalofPMOStransistorQ
21
isdisplacedtowardtheV-bus,
thereby reducing the channel resistance of Q
21
. As a
consequence, there is an incremental increase in current flow
through Q
20
, R
12
, Q
21
, D
6
, R
7
, and the base of Q
16
. As a
result, Q
16
sinks current from Terminal 6 in direct response to
the incremental change in output voltage caused by Q
18
. This
sink current flows regardless of load; any excess current is
internally supplied by the emitter-follower Q
18
. Short circuit
protection of the output circuit is provided by Q
19
, which is
driven into conduction by the high voltage drop developed
across R
11
under output short circuit conditions. Under these
conditions, the collector of Q
19
diverts current from Q
4
so as to
reduce the base current drive from Q
17
, thereby limiting current
flow in Q
18
to the short circuited load terminal.
Bias Circuit
Quiescent current in all stages (except the dynamic current
sink) of the CA3140 is dependent upon bias current flow in R
1
.
The function of the bias circuit is to establish and maintain
constant current flow through D
1
, Q
6
, Q
8
and D
2
. D
1
is a diode
connected transistor mirror connected in parallel with the base
emitterjunctionsofQ
1
,Q
2
,andQ
3
.D
1
maybeconsideredasa
current sampling diode that senses the emitter current of Q
6
and automatically adjusts the base current of Q
6
(via Q
1
) to
maintain a constant current through Q
6
, Q
8
, D
2
. The base
currents in Q
2
, Q
3
are also determined by constant current flow
D
1
. Furthermore, current in diode connected transistor Q
2
establishes the currents in transistors Q
14
and Q
15
.
Typical Applications
Wide dynamic range of input and output characteristics with
the most desirable high input impedance characteristics is
achieved in the CA3140 by the use of an unique design based
upon the PMOS Bipolar process. Input common mode voltage
range and output swing capabilities are complementary,
allowing operation with the single supply down to 4V.
The wide dynamic range of these parameters also means
that this device is suitable for many single supply
applications, such as, for example, where one input is driven
below the potential of Terminal 4 and the phase sense of the
output signal must be maintained – a most important
consideration in comparator applications.
CA3140, CA3140A
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| CA3140AS | H8/SLP Series, 38024R group, 32 Kbytes Flash ROM, 80-QFP package; Vcc= 2.7 to 3.6 volts, Temp= -40 to 85 C; Package: PRQP0080JB-A |
| CA3140AT | 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output |
| CA3140E | 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output |
| CA3140M | 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output |
| CA3140M96 | 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CA3140AM96 | 功能描述:IC OP AMP 4.5MHZ BIMOS 8-SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:2pA 電壓 - 輸入偏移:1000µV 電流 - 電源:85µA 電流 - 輸出 / 通道:20mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:680 (CN2011-ZH PDF) 其它名稱:MCP6L04T-E/SLCT |
| CA3140AMZ | 功能描述:運算放大器 - 運放 OPAMP 4.5MHZ LWBIAS RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| CA3140AMZ96 | 功能描述:運算放大器 - 運放 OPAMP 4 5MHZ LWBIASEL RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| CA3140AS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output |
| CA3140AT | 制造商:Harris Corporation 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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