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參數(shù)資料
| 型號(hào)： | CA3140AMZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 22/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP BIMOS 4.5MHZ 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 9 V/µs |
| 增益帶寬積： | 4.5MHz |
| 電流 - 輸入偏壓： | 10pA |
| 電壓 - 輸入偏移： | 2000µV |
| 電流 - 電源： | 4mA |
| 電流 - 輸出 / 通道： | 40mA |
| 電壓 - 電源，單路/雙路(±)： | 4 V ~ 36 V，±2 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1233 (CN2011-ZH PDF) |
8
FN957.10
July 11, 2005
Bandwidth and Slew Rate
For those cases where bandwidth reduction is desired, for
example, broadband noise reduction, an external capacitor
connected between Terminals 1 and 8 can reduce the open
loop -3dB bandwidth. The slew rate will, however, also be
proportionally reduced by using this additional capacitor.
Thus, a 20% reduction in bandwidth by this technique will
also reduce the slew rate by about 20%.
Figure 5 shows the typical settling time required to reach
1mV or 10mV of the final value for various levels of large
signal inputs for the voltage follower and inverting unity gain
amplifiers.
The exceptionally fast settling time characteristics are largely
due to the high combination of high gain and wide bandwidth
of the CA3140; as shown in Figure 6.
Input Circuit Considerations
As mentioned previously, the amplifier inputs can be driven
below the Terminal 4 potential, but a series current limiting
resistor is recommended to limit the maximum input terminal
current to less than 1mA to prevent damage to the input
protection circuitry.
Moreover, some current limiting resistance should be
provided between the inverting input and the output when
FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
3
2
4
CA3140
7
6
LOAD
RL
RS
MT2
MT1
30V
NO LOAD
120VAC
3
2
4
CA3140
7
6
V+
+HV
LOAD
RL
FIGURE 5A. WAVEFORM
FIGURE 5B. TEST CIRCUITS
FIGURE 5. SETTLING TIME vs INPUT VOLTAGE
SETTLING TIME (
s)
0.1
IN
PUT
V
O
L
T
A
G
E
(V)
1.0
10
SUPPLY VOLTAGE: VS = ±15V
TA = 25
oC
1mV
10mV
1mV
10mV
FOLLOWER
INVERTING
LOAD RESISTANCE (RL) = 2k
LOAD CAPACITANCE (CL) = 100pF
10
8
6
4
2
0
-2
-4
-6
-8
-10
10mV
3
2
CA3140
6
SIMULATED
LOAD
4
-15V
0.1
F
5.11k
0.1
F
7
+15V
5k
2k
100pF
5k
INVERTING
SETTLING POINT
200
4.99k
D1
1N914
D2
1N914
2
CA3140
6
SIMULATED
LOAD
4
-15V
0.1
F
0.1
F
7
+15V
2k
100pF
0.05
F
2k
3
10k
FOLLOWER
CA3140, CA3140A
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