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參數(shù)資料
| 型號： | CA3240E1 |
| 元件分類： | 通用總線功能 |
| 英文描述： | 12 STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDERS |
| 中文描述： | 集成電路雙運算放大器 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 342K |
| 代理商： | CA3240E1 |
3-118
Common-Mode Rejection Ratio
CMRR
32
32
μ
V/V
dB
90
90
Common-Mode Input Voltage Range (See Figure 25)
V
ICR
-0.5
-0.5
V
2.6
2.6
V
Power Supply Rejection Ratio
PSRR
31.6
31.6
μ
V/V
dB
90
90
Maximum Output Voltage (See Figures 24, 25)
V
OM
+
V
OM
-
I
OM
+
I
OM
-
SR
3
3
V
0.3
0.3
V
Maximum Output Current
Source
20
20
mA
Sink
1
1
mA
V/
μ
s
MHz
Slew Rate (See Figure 15)
7
7
Gain Bandwidth Product (See Figure 14)
f
T
I+
4.5
4.5
Supply Current (See Figure 16)
4
4
mA
Device Dissipation
P
D
20
20
mW
Electrical Specifications
For Equipment Design, at V+ = 5V, V- = 0V, T
A
= 25
o
C, Unless Otherwise Specified
(Continued)
PARAMETER
SYMBOL
TYPICAL VALUES
UNITS
CA3240A
CA3240
Test Circuits and Waveforms
FIGURE 1A. SMALL SIGNAL RESPONSE
FIGURE 1B. LARGE SIGNAL RESPONSE
FIGURE 1C. TEST CIRCUIT
FIGURE 1. SPLIT-SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS
50mV/Div., 200ns/Div.
Top Trace: Input, Bottom Trace: Output
5V/Div., 1
μ
s/Div.
Top Trace: Input, Bottom Trace: Output
2k
10k
CA3240
-
+15V
-15V
0.1
μ
F
0.1
μ
F
100pF
SIMULATED
LOAD
2k
0.05
μ
F
+
BW (-3dB) = 4.5MHz
SR = 9V/
μ
s
CA3240, CA3240A
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| CA3240EX | 制造商:Rochester Electronics LLC 功能描述:BIMOS DUAL OP AMP MOSFET IN BIP OUT BURN-IN 8 PDIP COM - Bulk |
| CA3240EZ | 功能描述:運算放大器 - 運放 OPAMP 2X 4.5MHZ LWBI AS 0.05NA 8PDIP RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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