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參數(shù)資料
| 型號： | CA95C09-20CT |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 33/42頁 |
| 文件大?。?/td> | 180K |
| 代理商： | CA95C09-20CT |
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Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-63
Load Clear IVE Register Through Master Port (85H)
Load Clear IVD Register Through Master Port (84H)
These commands (available in Multiplexed Control Mode
only) are virtually identical to Load Clear E (or D) Key
Through Master Port, except that the data written to the Input
Register address is transferred to either the Initialization
Vector for Encryption (IVE) or Decryption (IVD) Register
instead of a Key Register and no parity checking takes place.
The Command Pending bit (S6) is a “1” during the entire
loading process.
Load Encrypted IVE Register Through Master Port
(A5H)
Load Encrypted IVD Register Through Master Port
(A4H)
These commands are similar to the Load Encrypted E (or D)
Key Through Master Port commands. The data ow
specication set in the Mode Register is overridden and the
eight initial vector bytes are decrypted using the Decryption
(D) Key and the Electronic Code Book algorithm. The
resulting clear initial vector bytes are routed into the
appropriate Initialization Vector Register, and no parity
checking occurs. The Busy bit (S5) does not go to “1” during
the decryption process, but Command Pending bit (S6) will
be “1” during the entire decryption-and-load operation.
Read Clear IVE Register Through Master Port (8DH)
Read Clear IVD Register Through Master Port (8CH)
The effect of these commands (available in Multiplexed
Control Mode only) is to override the data ow specications
set in the Mode Register and to allow the appropriate
Initialization Vector Register to be read from the Output
Register through the Master Port. When executing this
instruction, each IV Register appears as eight bytes of FIFO
storage. The rst byte of data will be available six clocks
after the loading of the Command Register. The Command
Pending bit will be set to “1” and will remain a “1” until
sometime after the eighth byte is read out. The host system
has the responsibility to read out exactly eight bytes.
Read Encrypted IVE Register Through Master Port
(A9H)
Read Encrypted IVD Register Through Master Port
(A8H)
The effect of these commands (in Multiplexed Control Mode
only) is to override the specications set in the Mode
Register and to encrypt the contents of the specied
Initialization Vector Register using the Electronic Code Book
algorithm and the Encrypt (E) Key. The resulting eight bytes
of cipher text can be read from the Output Register through
the Master Port. The Busy bit (S5) will be “1” during the
encryption process,
when it goes to “0, “the encrypted
initial vector bytes are ready to be read out. The Command
Pending bit (S6) will be “1” during the entire encryption-
and-output process, and will go to “0” when the eighth byte
is read out. The host system is responsible for reading out
exactly eight bytes.
Encrypt with Master (M) Key (39H)
This command (available in Multiplexed Control Mode only)
overrides the data ow specications set in the Mode
Register and causes the DCP to write eight bytes of data to
the Input Register via the Master Port. After the eighth byte
has been received, the data is encrypted using the Master (M)
Key and then routed to the Output Register, where it may be
read out through the Master Port. The Command Pending
(S6) and Busy (S5) bits are used to sense the three phases of
this operation. Command Pending goes to “1” as soon as the
Input Register can accept data. When exactly eight bytes
have been entered, the Busy bit will got to “1” until the
encryption process is complete. When Busy goes to “0”, the
encrypted data is available to be read out. Command Pending
will return to “0” when the eighth byte has been read.
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