參數(shù)資料
型號(hào)： CA95C09-5CT
元件分類： 加密電路
英文描述： TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44
封裝： TQFP-44
文件頁(yè)數(shù)： 38/42頁(yè)
文件大小： 180K
代理商： CA95C09-5CT
Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-29
MALE
27
30
–
I
Master Port Address Latch Enable: (For CA95C68) In Multiplexed Control
Mode (C/K LOW), an active HIGH signal on this pin indicates the presence of
valid address and chip select information at the Master Port. This information
will be latched internally on the falling edge of MALE. When C/K is HIGH
(Direct Control Mode), MALE has no affect on DCP operation.
26
29
–
I
Master Port Read: (For CA95C68) This active LOW input is used with a
valid
to indicate that data is to be output on the Master Port bus.
Master Port Read (
) and Master Port Write (
) are normally
mutually exclusive; if both become active simultaneously, the DCP is reset to
ECB Mode and all ags go inactive.
28
31
–
I
Master Port Write: (For CA95C68) This active low input signal indicates to
the DCP that valid data is present on MP7-MP0 for an input operation. The
rising edge of
latches the data into the selected internal register. If
and
both go LOW simultaneously, the DCP is reset.
27
30
–
I
Master Port Address Strobe: (For CA95C18) In Multiplexed Control Mode
(C/K HIGH), a LOW on
indicates the presence of a valid chip select
signal and address information. This information will be latched on the rising
edge of
. In Direct Control Mode,
has no affect on the DCP
operation. The DCP will be reset if
and
both go low
simultaneously.
26
29
–
I
Master Port Data Strobe: (For CA95C18) This active low input is used in
conjunction with a valid Master Port Chip Select (
) to indicate that
valid data is present on the MP7-MP0 bus for an input operation or that data
is to be placed on the Master Port Bus during output.
and
are
mutually exclusive; if they both go active simultaneously, the DCP is reset to
ECB mode and all ags go inactive.
MR/W
28
31
–
I
Master Port Read/Write: (For CA95C18) This input signal indicates to the
DCP whether the current Master Port operation is a read (HIGH) where data
is transferred from the device, or a write (LOW) where data is stored to an
internal register. MR/W is not latched internally and must be held stable while
is LOW.
Table 3-2 : Pin Description Cont'd
Symbol
95C68/18
95C09
TYPE
Name and Function
PDIP
PLCC
TQFP
MRD
MCS
MRD
MWR
MRD
MAS
MDS
MCS
MDS
MAS
MDS
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