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參數(shù)資料
| 型號： | CAT1022ZI-28-GT3 |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | ROHS COMPLIANT, MO-187, MSOP-8 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大小： | 239K |
| 代理商： | CAT1022ZI-28-GT3 |
CAT1021, CAT1022, CAT1023
Catalyst Semiconductor, Inc.
5
Doc. No. MD-3009 Rev. M
Characteristics subject to change without notice
CAPACITANCE
TA = 25C, f = 1.0MHz, VCC = 5V
Symbol
Test
Test Conditions
Max
Units
COUT
Output Capacitance
VOUT = 0V
8
pF
CIN
(1)
Input Capacitance
VIN = 0V
6
pF
AC CHARACTERISTICS
V
CC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
(2)
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
400
kHz
tSP
Input Filter Spike Suppression (SDA, SCL)
100
ns
tLOW
Clock Low Period
1.3
s
tHIGH
Clock High Period
0.6
s
tR
(1)
SDA and SCL Rise Time
300
ns
tF
(1)
SDA and SCL Fall Time
300
ns
tHD; STA
Start Condition Hold Time
0.6
s
tSU; STA
Start Condition Setup Time (for a Repeated Start)
0.6
s
tHD; DAT
Data Input Hold Time
0
ns
tSU; DAT
Data Input Setup Time
100
ns
tSU; STO
Stop Condition Setup Time
0.6
s
tAA
SCL Low to Data Out Valid
900
ns
tDH
Data Out Hold Time
50
ns
tBUF
(1)
Time the Bus must be Free Before a New Transmission Can Start
1.3
s
tWC
(3)
Write Cycle Time (Byte or Page)
5
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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| CAT1022ZI-28TE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
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