參數(shù)資料
型號: CAT1026
英文描述: Dual Voltage Supervisory Circuit with I2C Serial 2K CMOS EEPROM. Reset Active High & Low. Auxiliary Voltage Monitor
中文描述: 雙電壓監(jiān)控電路與I2C串行2K的CMOS EEPROM中。復(fù)位高有效
文件頁數(shù): 6/17頁
文件大?。?/td> 114K
代理商: CAT1026
6
CAT1026, CAT1027
Preliminary Information
Doc. No. 3010, Rev. G
VOLTAGE MONITOR AND RESET CIRCUIT AC CHARACTERISTICS
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Test Conditions according to
AC Test Conditions
table.
Power-up, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to
AC Test Conditions
Table.
Power-Down, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to
AC Test Conditions
Table.
V
CC
Glitch Reference Voltage = V
THmin
; Based on characterization data.
0 < V
SENSE
V
CC
, V
LOW
Output Reference Voltage and Load according to
AC Test Conditions
Table.
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified memory operation can be initiated.
Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to V
CC
+ 1 V.
AC TEST CONDITIONS
l
b
m
y
S
r
e
t
e
m
a
r
a
P
t
e
o
n
T
s
n
o
C
n
M
p
y
T
x
a
M
s
U
t
T
S
R
U
P
t
o
e
m
i
t
s
e
R
2
e
N
0
3
1
0
0
2
0
7
2
s
m
t
1
D
P
R
V
H
T
V
C
y
a
D
t
p
O
T
E
S
E
R
o
3
e
N
5
s
μ
t
H
C
T
G
t
W
t
R
C
h
W
e
s
P
t
e
R
h
c
G
6
,
e
N
0
3
s
n
D
t
o
e
m
i
g
o
d
h
c
W
1
e
N
0
6
1
c
e
s
2
D
P
V
E
S
N
E
S
V
o
W
O
L
y
a
D
5
e
N
5
s
μ
G
N
I
M
I
T
P
U
-
R
E
W
O
P
7
l
b
m
y
S
r
e
t
e
m
a
r
a
P
t
e
o
n
T
s
n
o
C
n
M
p
y
T
x
a
M
s
U
t
R
U
P
n
o
p
O
d
a
e
R
o
p
U
-
w
o
P
0
7
2
s
m
t
W
U
P
n
o
p
O
e
W
o
p
U
-
w
o
P
0
7
2
s
m
RELIABILITY CHARACTERISTICS
Symbol
N
END(6)
Parameter
Reference Test Method
Min
Max
Units
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR(6)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP(6)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
I
LTH(6)(8)
Latch-Up
JEDEC Standard 17
100
mA
r
e
m
a
r
a
P
s
n
o
n
o
C
s
e
g
a
V
e
s
P
t
p
n
V
2
C
1
C
V
8
o
C
C
s
e
m
i
l
F
d
n
a
e
s
R
t
p
n
s
n
0
s
e
g
a
V
e
c
n
e
R
t
p
n
V
3
C
C
V
7
,
C
C
s
e
g
a
V
e
c
n
e
R
t
p
O
V
5
C
C
d
a
o
L
t
p
O
I
:
0
1
c
o
C
L
=
S
t
e
C
L
F
O
p
;
A
m
3
=
0
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