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參數(shù)資料
| 型號(hào)： | CAT1161LI25 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001, DIP-8 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大小： | 188K |
| 代理商： | CAT1161LI25 |
CAT1161, CAT1162
2007 Catalyst Semiconductor, Inc.
9
Doc. No. 3002 Rev. F
Characteristics subject to change without notice
Acknowledge Polling
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1161/2 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the CAT1161/2 is still busy with the write operation,
no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to
protect against inadvertent memory array program-
ming. If the WP pin is tied to VCC, the entire memory
array is protected and becomes read only. The
CAT1161/2
will
accept
both
slave
and
byte
addresses, but the memory location accessed is
protected from programming by the device’s failure
to send an acknowledge after the first byte of data is
received.
READ OPERATIONS
The READ operation for the CAT1161/2 is initiated in the
same manner as the write operation with one exception,
that R/W
bit is set to one. Three different READ ope–
rations are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
Immediate/Current Address Read
The CAT1161/2 address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to
address N, the READ immediately following would
access data from address N+1. For all devices,
N=E=2047. The counter will wrap around to Zero and
continue to clock out valid data for the 16K devices.
After
the
CAT1161/2
receives
its
slave
address
information (with the R/W
bit set to one), it issues an
acknowledge, then transmits the 8-bit byte requested.
The master device does not send an acknowledge, but
will generate a STOP condition.
Figure 9. Immediate Address Read Timing
SCL
SDA
8TH BI T
STOP
NO ACK
DATA OUT
89
SLAVE
ADDRESS
S
A
C
K
DATA
N
O
A
C
K
S
T
O
P
BUS ACTIVIT Y:
MASTER
SDA LINE
S
T
A
R
T
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT1161LI-25 | 制造商:Catalyst Semiconductor 功能描述: |
| CAT1161LI-25-G | 功能描述:監(jiān)控電路 CPU w/16K RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT1161LI28 | 功能描述:監(jiān)控電路 16K I2C Memory w/WDT RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT1161LI-28 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT1161LI-28-G | 功能描述:監(jiān)控電路 CPU w/16K RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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