參數(shù)資料
型號: CAT130041SWI-GT3
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8
文件頁數(shù): 10/14頁
文件大?。?/td> 310K
代理商: CAT130041SWI-GT3
CAT130xx
2007 Catalyst Semiconductor, Inc.
5
Doc. No. 1121 Rev. A
Characteristics subject to change without notice
PIN DESCRIPTION
RESET/RESET
: The reset output is available in two
versions: CMOS Active Low (CAT130xx9) and CMOS
Active High (CAT130xx1). Both versions are push-pull
outputs for high efficiency.
DI: The serial data input pin accepts op-codes,
addresses and data. The input data is latched on the
rising edge of the SK clock input.
DO: The serial data output pin is used to transfer data
out of the device. The data is shifted out on the rising
edge of the SK clock.
SK: The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT130xx device.
CS: The chip select input pin is used to enable/disable
the CAT130xx. When CS is high, the device is
selected and accepts op-codes, addresses and data.
Upon receiving a Write or Erase instruction, the falling
edge of CS will start the internal write cycle to the
selected memory location.
ORG: The memory organization input selects the memory
configuration as either register of 16 bits (ORG tied to
VCC or floating) or 8 bits (ORG connected to GND).
DEVICE OPERATION
The CAT130xx products combine the accurate
voltage monitoring capabilities of a standalone voltage
supervisor with the high quality and reliability of
standard EEPROMs from Catalyst Semiconductor.
RESET CONTROLLER DESCRIPTION
The reset signal is asserted LOW for the CAT130xx9
and HIGH for the CAT130xx1 when the power supply
voltage falls below the threshold trip voltage
and remains asserted for at least 140ms (tPURST) after
the power supply voltage has risen above the
threshold. Reset output timing is shown in Figure 1.
The CAT130xx devices protect
μPs against brownout
failure. Short duration VCC transients of 4μsec or less and
100mV amplitude typically do not generate a Reset pulse.
Figure 2 shows the maximum pulse duration of
negative-going VCC transients that do not cause a
reset condition. As the amplitude of the transient goes
further below the threshold (increasing VTH - VCC), the
maximum pulse duration decreases. In this test, the
VCC starts from an initial voltage of 0.5V above the
threshold and drops below it by the amplitude of the
overdrive voltage (VTH - VCC).
Figure 2. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
Figure 1. RESET Output Timing
VCC
PURST
t
PURST
t
RPD
t
RVALID
V
TH
RESE T
CAT130xx9
CAT130xx1
RPD
t
T
R
AN
SI
EN
T
D
U
R
AT
IO
N
[
s
]
RESET OVERDRIVE VTH - VCC [mV]
TAMB = 25C
CAT130xxM
CAT130xxZ
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