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參數(shù)資料
| 型號(hào)： | CAT1320YI-45TSSOP |
| 英文描述： | Supervisory Circuits with I2C Serial 32K CMOS EEPROM |
| 中文描述： | 監(jiān)控電路，帶有I2C串行EEPROM中的CMOS 32K的 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 496K |
| 代理商： | CAT1320YI-45TSSOP |
10
CAT1320, CAT1321
Advance Information
Doc. No. 25085, Rev. 00
Figure 9. Page Write Timing
*=Don’t Care Bit
Figure 8. Byte Write Timing
*=Don’t Care Bit
Page Write
The CAT1320/21 writes up to 64 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the byte
write operation, however instead of terminating after the
initial byte is transmitted, the Master is allowed to send up
to
additional 63 bytes. After each byte has been
transmitted, the CAT1320/21 will respond with an
acknowledge and internally increment the lower order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1320/21 in a single write cycle.
*
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7–A0
BYTE ADDRESS
A
C
K
** *
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7–A0
BYTE ADDRESS
DATA n+63
DATA
A
C
K
S
T
O
P
A
C
K
DATA n
A
C
K
P
A
C
K
****
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| CAT1320ZD2I-25-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
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| CAT1320ZD2I-42-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
| CAT1320ZD2I-45-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
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