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參數(shù)資料
| 型號： | CAT1320ZD2I-30TE13 |
| 英文描述： | 2 PR #24 FEP FLMRST RoHS Compliant: Yes |
| 中文描述： | 監(jiān)控電路，帶有I2C串行EEPROM中的CMOS 32K的 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 496K |
| 代理商： | CAT1320ZD2I-30TE13 |
5
Advance Information
CAT1320, CAT1321
Doc No. 25085, Rev. 00
RESET CIRCUIT A.C. CHARACTERISTICS
Notes:
1.
Test Conditions according to “AC Test Conditions” table.
2.
Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
3.
Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
4.
VCC Glitch Reference Voltage = VTHmin; Based on characterization data
5.
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6.
tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
AC TEST CONDITIONS
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
NEND(1)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
TDR(1)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP(1)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
ILTH(1)(2)
Latch-Up
JEDEC Standard 17
100
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Notes:
1.
This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2.
Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V.
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