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參數資料
| 型號： | CAT150089RWI-GT3 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | PROM |
| 英文描述： | 8K X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOIC-8 |
| 文件頁數： | 13/15頁 |
| 文件大小： | 174K |
| 代理商： | CAT150089RWI-GT3 |
CAT15008, CAT15016
2008 SCILLC. All rights reserved.
7
Doc. No. MD-1125 Rev. B
Characteristics subject to change without notice
STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
The RDY
(Ready) bit indicates whether the device is
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the
user with the WRSR command and are non-volatile. The
user is allowed to protect a quarter, one half or the entire
memory, by setting these bits according to Table 3. The
protected blocks then become read-only.
The WPEN (Write Protect Enable) bit acts as an enable
for the WP
pin. Hardware write protection is enabled
when the WP
pin is low and the WPEN bit is 1. This
condition prevents writing to the status register and to
the
block
protected
sections
of
memory.
While
hardware write protection is active, only the non-block
protected memory can be written. Hardware write
protection is disabled when the WP
pin is high or the
WPEN bit is 0. The WPEN bit, WP
pin and WEL bit
combine to either permit or inhibit Write operations, as
detailed in Table 4.
Table 2. Status Register
7
6
5
4
3
2
1
0
WPEN
0
BP1
BP0
WEL
RDY
Table 3. Block Protection Bits
Status Register Bits
BP1
BP0
Array Address Protected
Protection
0
None
No Protection
15008: 0300-03FF
0
1
15016: 0600-07FF
Quarter Array Protection
15008: 0200-03FF
1
0
15016: 0400-07FF
Half Array Protection
15008: 0000-03FF
1
15016: 0000-07FF
Full Array Protection
Table 4. Write Protect Enable Operation
WPEN
WP
WEL
Protected Blocks
Unprotected Blocks
Status Register
0
X
0
Protected
0
X
1
Protected
Writable
1
Low
0
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
X
High
1
Protected
Writable
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CAT150089SWI-G | 功能描述:監(jiān)控電路 w/8k SPI RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT150089SWI-GT3 | 功能描述:監(jiān)控電路 w/8k SPI RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT150161MWI-GT3 | 功能描述:監(jiān)控電路 SUP W/16K SPI EEPROM RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT150169MWI-GT3 | 功能描述:監(jiān)控電路 SUP W/16K SPI EEPROM RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT150169SWI-GT3 | 功能描述:監(jiān)控電路 SUP W/16K SPI EEPROM RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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