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參數(shù)資料
| 型號： | CAT24C64ZE-T3 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | PROM |
| 英文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | 3 X 3 MM, HALOGEN FREE, BFR FREE AND ROHS COMPLIANT, MO-187, MSOP-8 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 175K |
| 代理商： | CAT24C64ZE-T3 |
CAT24C64
http://onsemi.com
3
Table 5. A.C. CHARACTERISTICS
Symbol
Parameter
Standard
VCC = 1.7 V 5.5 V
Fast
VCC = 1.7 V 5.5 V
FastPlus (Note 9)
VCC = 2.5 V 5.5 V
TA = 405C to +855C
Units
Min
Max
Min
Max
Min
Max
FSCL
Clock Frequency
100
400
1,000
kHz
tHD:STA
START Condition Hold Time
4
0.6
0.25
ms
tLOW
Low Period of SCL Clock
4.7
1.3
0.45
ms
tHIGH
High Period of SCL Clock
4
0.6
0.40
ms
tSU:STA
START Condition Setup Time
4.7
0.6
0.25
ms
tHD:DAT
Data In Hold Time
0
ms
tSU:DAT
Data In Setup Time
250
100
50
ns
SDA and SCL Rise Time
1,000
300
100
ns
SDA and SCL Fall Time
300
100
ns
tSU:STO
STOP Condition Setup Time
4
0.6
0.25
ms
tBUF
Bus Free Time Between
STOP and START
4.7
1.3
0.5
ms
tAA
SCL Low to Data Out Valid
3.5
0.9
0.40
ms
tDH
Data Out Hold Time
100
50
ns
Noise Pulse Filtered at SCL
and SDA Inputs
100
ns
tSU:WP
WP Setup Time
0
ms
tHD:WP
WP Hold Time
2.5
1
ms
tWR
Write Cycle Time
5
ms
Power-up to Ready Mode
1
0.1
1
ms
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
9. FastPlus (1 MHz) speed class available for product revision “F”. The die revision “F” is identified by letter “F” or a dedicated marking code
on top of the package.
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
≤ 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels
0.5 x VCC
Output Load
Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
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