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參數(shù)資料
| 型號： | CAT24FC17ZETE13REV-F |
| 元件分類： | DRAM |
| 英文描述： | 16-kb I2C Serial EEPROM |
| 中文描述： | 16 KB的的I2C串行EEPROM |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 92K |
| 代理商： | CAT24FC17ZETE13REV-F |
CAT24C01B
3
Doc. No. 25085-00 7/99 S-1
A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, CL=1TTL Gate and 100pF (unless otherwise specified).
Read & Write Cycle Limits
Symbol
Parameter
1.8V, 2.5V
4.5V-5.5V
Min.
Max.
Min.
Max.
Units
FSCL
Clock Frequency
100
400
kHz
TI(1)
Noise Suppression Time
100
ns
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
3.5
1
s
and ACK Out
tBUF(1)
Time the Bus Must be Free Before
4.7
1.2
s
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
4
0.6
s
tLOW
Clock Low Period
4.7
1.2
s
tHIGH
Clock High Period
4
0.6
s
tSU:STA
Start Condition Setup Time
4.7
0.6
s
(for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
0
ns
tSU:DAT
Data In Setup Time
250
100
ns
tR(1)
SDA and SCL Rise Time
1
0.3
s
tF(1)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
4.7
0.6
s
tDH
Data Out Hold Time
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its input.
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
Units
tWR
Write Cycle Time
10
ms
Power-Up Timing(1)(2)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
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