參數(shù)資料
型號(hào): CAT24WC129LATE13
英文描述: 128K-Bit I2C Serial CMOS EEPROM
中文描述: 128K的位I2C串行CMOS EEPROM的
文件頁數(shù): 4/9頁
文件大小: 591K
代理商: CAT24WC129LATE13
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Figure 3. Start/Stop Timing
CAT24WC129
4
Doc. No. 1079, Rev. V
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
START BIT
SDA
STOP BIT
SCL
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC129 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
PIN DESCRIPTIONS
SCL:
Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA:
Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
open drain or open collector outputs.
WP:
Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the top
1/4 array of memory (locations 3000H to 3FFFH) is write
protected. When left floating, memory is unprotected.
相關(guān)PDF資料
PDF描述
CAT24WC129LI-1.8TE13 128K-Bit I2C Serial CMOS EEPROM
CAT24WC129LI-3TE13 128K-Bit I2C Serial CMOS EEPROM
CAT24WC129LITE13 128K-Bit I2C Serial CMOS EEPROM
CAT24WC129LTE13 128K-Bit I2C Serial CMOS EEPROM
CAT24WC129P-1.8TE13 128K-Bit I2C Serial CMOS EEPROM
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