參數(shù)資料
型號: CAT24WC164ZITE13
英文描述: 16K-Bit Serial EEPROM, Cascadable
中文描述: 16K的位串行EEPROM,可級聯(lián)
文件頁數(shù): 4/13頁
文件大?。?/td> 647K
代理商: CAT24WC164ZITE13
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Figure 3. Start/Stop Timing
CAT24WC164
4
Doc. No. 1026, Rev. J
FUNCTIONAL DESCRIPTION
The CAT24WC164 supports the I
2
C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC164
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated. A
maximum of 8 devices may be connected to the bus as
determined by the device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24WC164 serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SDA:
Serial Data/Address
The CAT24WC164 bidirectional serial data/address pin
SDA pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These inputs set device address when cascading multiple
devices. When these pins are left floating the default
values are zeros.
A maximum of eight devices can be cascaded. If only
one CAT24WC164 is addressed on the bus, all three
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL
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